What is the correct order of ADC control signals for this design?

Address on PB0-2, ALE pulse after at least 50 ns, START after about 2.5 us, wait for EOC

START first, then address, then ALE

OE first, then address, then START

When is the output latch enabled (PB6) and the data read?

After EOC goes high; then port A is read and OE cleared

2072 Kartik · 8 marks

8-channel ADC interface with 8255 and 8085

Short answer

Port A=80H, Port B=81H, Port C=82H, Control register=83H. The control word is 98H (mode 0, port A input, port B output, PC5 input). Channel 4 address 04H is sent on PB0-2, ALE on PB4, START on PB3, OE on PB6, EOC read from PC5.

To convert an analog signal into digital form, 8-bit ADC is used. The ADC has eight input channels, and channel four is used to capture the incoming analog signal. The address of the desired channel is sent through pins PB0, PB1 and PB2. After at least 50-nanoseconds, this address must be latched. The latching signal is sent using PB4. After another 2.5-microseconds, PB3 is used to initiate the conversion process. The completion of the process is signaled via PC5. The output latch of the ADC can be enabled through PB6, and digital data can be read through port A of 8255-PPI. (i) Draw a circuit showing the interfacing of the ADC module, 8255-PPI and 8085 microprocessor on the basis of the connections described above. (ii) Draw the timing waveforms of all the control and data signals involved in the process. (iii) Provide a flowchart that depicts the ADC process. (iv) Derive port addresses from your circuit diagram and provide the control word.

Assumptions

The 8085 is I/O mapped. The 8255 is selected by A7-A2 = 100000, so Port A = 80H, Port B = 81H, Port C = 82H, Control = 83H. Channel 4 = address 100 on PB2 PB1 PB0.

(i) Interfacing circuit

 8085                     8255A                   ADC (8-ch, 8-bit)
 AD0-AD7 (data) -------> D0-D7
 IOR' -> RD'   IOW' -> WR'  RESET OUT -> RESET
 A0,A1 (latched) -> A0,A1
 A7..A2 decoder -> CS'
                          PB0 ------------------> ADD A
                          PB1 ------------------> ADD B
                          PB2 ------------------> ADD C
                          PB3 ------------------> START
                          PB4 ------------------> ALE
                          PB6 ------------------> OE
                          PC5 <------------------ EOC
                          PA0-PA7 <-------------- D0-D7 (output latch)
                          Clock: CLK OUT of 8085 divided to 640 kHz

Sequence of operation

Send channel address 100 (04H) on PB0-PB2.
After at least 50 ns, raise ALE (PB4) to latch the address.
After 2.5 us, raise START (PB3). The conversion begins on its falling edge.
Wait for EOC (PC5) to go high.
Raise OE (PB6) and read port A. Then clear OE.

(ii) Timing waveforms

 ADD (PB0-2) ---<  100 (channel 4)  >----------------------
 ALE  (PB4)  ___________/----\______________________________
 START (PB3) ______________________/----\____________________
 EOC  (PC5)  ____________________________\_____________/-----
                     >=50ns  >=2.5us      conversion (~100us)
 OE   (PB6)  ______________________________________/---\____
 Data (PA)   ---------------------------------------< valid >-

(iii) Flowchart

 START -> Initialise 8255 (control word)
       -> Output channel address 04H to PB0-PB2
       -> Set ALE = 1 (PB4), then 0   (latch address)
       -> Delay >= 2.5 us
       -> Set START = 1 (PB3), then 0 (start conversion)
       -> Is EOC (PC5) = 1 ? -- no --> wait
       -> yes: Set OE = 1 (PB6)
       -> Read port A (digital data)
       -> OE = 0 -> END

(iv) Control word and program

Port A input (D4 = 1), port B output (D1 = 0), PC5 is in upper port C and is an input (D3 = 1), lower C unused (D0 = 0), mode 0 for both groups: 1001 1000 = 98H.

        MVI A,98H
        OUT 83H
        MVI A,04H       ; channel 4 address
        OUT 81H
        MVI A,14H       ; ALE = 1 (PB4) with address
        OUT 81H
        MVI A,04H       ; ALE = 0
        OUT 81H
        NOP
        NOP             ; > 2.5 us delay (at 3 MHz, 3 x 1.33 us = 4 us)
        NOP
        MVI A,0CH       ; START = 1 (PB3) with address
        OUT 81H
        MVI A,04H       ; START = 0
        OUT 81H
WAIT:   IN 82H
        ANI 20H         ; EOC (PC5)
        JZ WAIT
        MVI A,44H       ; OE = 1 (PB6)
        OUT 81H
        IN 80H          ; read data
        MVI A,04H
        OUT 81H         ; OE = 0
        HLT

✓ Answer checked by Claude Sonnet 5.5

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