Which block does the 74LS138 decode in this design, and why are 81H and 82H inside it?

80H-87H, since A7 = 1 and A6-A3 = 0 are fixed and A2-A0 select within the block

Why is a 74LS373 latch enabled by ALE used first?

To separate the multiplexed low address byte A7-A0 from the data lines

To increase drive current of the data bus

Why does IO/M' go through an inverter to G2B'?

So the decoder is enabled only in I/O cycles

In OUT 82H, how does the output latch capture the data?

Y2' goes low, WR' low makes the NOR output high so the latch is transparent, then holds the data when WR' returns high

Y2' goes low and RD' enables the buffer

Y1' goes low and WR' enables the buffer

2070 Magh · 8 marks

Address decoding for input and output ports

Short answer

Use a 74LS138 block decoder with A2-A0 selecting outputs and A7 plus A6-A3 enabling it, gated by IO/M. Y1 and Y2 select ports 81H and 82H; combine with RD for input buffer enable and WR for output latch clock. IN 81H reads, OUT 82H writes.

Design the address decoding interface of an input port and output port for 8085 at 81 H and 82 H address. Use block decoder.

Peripheral (isolated) I/O is used, so the port address is the 8-bit address on A7–A0 and IO/M' must be high. A 74LS138 (3:8 decoder) is used as the block decoder: it decodes the block 80H–87H, and the two outputs Y1' and Y2' give the ports 81H and 82H.

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

Address decoding

Port	Address	A7 A6 A5 A4 A3	A2 A1 A0	Output
Input port	81H	1 0 0 0 0	0 0 1	Y1'
Output port	82H	1 0 0 0 0	0 1 0	Y2'

A2, A1, A0 are connected to the select inputs C, B, A of the decoder.
A7 is connected to enable G1 (must be 1).
A6, A5, A4, A3 go through a 4-input OR gate to enable G2A' (it is 0 only when all four are 0).
IO/M' goes through an inverter to G2B', so the decoder is enabled only in an I/O cycle (IO/M' = 1).

Circuit

 A2 --- C \
 A1 --- B  | 74LS138
 A0 --- A /
 A7 ---------- G1
 A6..A3 -[OR4]- G2A'
 IO/M' -[NOT]-- G2B'
                Y1' --+--[OR]-- to 74LS244
                      |   ^    enable (G')
                      |  RD'
                Y2' --[NOR]-- LE of 74LS373
                       ^
                      WR'
 
 Input : 74LS244 buffer, D0-D7 from device -> AD7-AD0
 Output: 74LS373 latch, AD7-AD0 -> D0-D7 to device

Working

IN 81H: the CPU puts 81H on A7–A0 and IO/M' = 1. Y1' goes low. When RD' also goes low, the OR gate output is low and enables the 3-state buffer, so the device data reaches the data bus.
OUT 82H: Y2' goes low. When WR' goes low the NOR gate output goes high; the latch is transparent and takes the data. When WR' returns high the output falls and the latch holds the data for the output device.

Other outputs of the decoder (Y0', Y3'–Y7') remain free for more ports in the block 80H–87H.

✓ Answer checked by Claude Opus 5.5 (high effort)

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Address decoding for input and output ports

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Circuit

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