- 2072 Kartik · 4 marks
Memory-mapped I/O design for 8085
Short answer
Memory-mapped I/O allows all memory instructions to access ports, supports up to 64K ports, and uses no separate I/O signals. For output block 1000H-1FFFH, decode A15-A12=0001 with MEMW'; for input block 3000H-3FFFH, decode 0011 with MEMR'. Use 74LS138 with A15,A13,A12 as inputs, A14 and IO/M as enables.
What benefit are obtained from a memory-mapped I/O design? Design an interface arrangement for 8085 microprocessor to map output ports in address space 1000H to 2000H and input ports in address space 3000H to 4000H.
Benefits of memory mapped I/O
- All memory reference instructions (LDA, STA, MOV M,A, ADD M, ANA M) can access ports, so data in ports can be processed directly without moving it to the accumulator.
- A large number of I/O ports is possible (up to 64K addresses) and all addressing modes are available.
- No separate I/O control signals (IOR', IOW') or special IN/OUT instructions are needed; ports use the same control signals as memory.
- Disadvantage: ports use up memory addresses and decoding needs the full 16-bit address.
Design
Assumption: output ports occupy the block 1000H-1FFFH and input ports the block 3000H-3FFFH (the end addresses 2000H and 4000H are taken as the beginning of the next blocks, because the given ranges can be selected exactly only in 4K blocks using A15-A12).
| Block | A15 A14 A13 A12 | Range | Signal |
|---|---|---|---|
| Output ports | 0 0 0 1 | 1000H-1FFFH | MEMW' |
| Input ports | 0 0 1 1 | 3000H-3FFFH | MEMR' |
Use a 74LS138 with inputs C = A15, B = A13, A = A12, and A14 on the enable G2A'. Enables: G1 = 1, G2A' = A14, G2B' = IO/M (so the decoder works only for memory cycles with A14 = 0). Output Y1 (A13 A12 = 01) -> output block; Y3 (A13 A12 = 11) -> input block. Output port select = Y1' OR WR'; this goes low during the write pulse and rises at its end, so it can clock a 74LS374 output latch. Input port select = Y3' OR RD', which enables a tri-state buffer (74LS244).
A15 -> C A13 -> B A12 -> A A14 -> G2A' IO/M -> G2B' +5V -> G1
Y1' --[OR]-- WR' --> clock of 74LS374 latch : output port (D0-D7 in)
Y3' --[OR]-- RD' --> enable of 74LS244 buffer : input port (D0-D7 out)
AD0-AD7 (after demultiplexing) are connected to the port data lines
Individual ports within each block are chosen using lower address lines (A0-A2), for example by another decoder.
✓ Answer checked by Claude Sonnet 5.5
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