Skip to main content

Full vs partial address decoding for memory

Short answer

Full address decoding is preferred because it gives each memory location a unique address, eliminates foldback images, and uses address space efficiently for expansion. For example, a 2K RAM at 0000H–07FFH decodes all upper address lines A15–A11 to select the chip only in that range.

Among full or partial address decoding, which method of address decoding do you choose while interfacing memory device? Give reasons with suitable example.

For interfacing memory I choose full (absolute, unique) address decoding.

Reasons

  1. Unique address: each location has exactly one address, so there is no ambiguity and no bus conflict when memories are expanded.
  2. Efficient use of address space: no image (foldback) addresses are wasted, so the maximum memory can be added later.
  3. Easy expansion and relocation: new chips can be placed in free blocks without conflicts.
  4. Simple software: programs and monitor routines use exactly one address map. This is needed for ROM at the reset vector and for operating systems.
  5. Partial decoding saves a few gates, but the saving is small in a memory system.

Example (8085, 2K x 8 RAM at 0000H-07FFH)

The chip has 11 address lines (A0-A10). The remaining lines A15-A11 are used to generate CS'.

  • Full decoding: CS' = A15 + A14 + A13 + A12 + A11 + IO/M (a 6-input OR gate). CS' is low only when all these inputs are 0, so the chip responds only at 0000H-07FFH.
  • Partial decoding: CS' = A15 only (low when A15 = 0). The chip responds at 0000H-07FFH, 0800H-0FFFH, ... 7800H-7FFFH (16 images), so the region 0800H-7FFFH cannot be used for other devices.
 A15..A11, IO/M --[6-input OR]--> CS'    A10..A0 --> chip A10..A0
 RD' -> OE'  WR' -> WE'

Partial decoding is acceptable only for very small systems or I/O ports where only a few devices exist.

✓ Answer checked by Claude Sonnet 5.5

Related questions

All Instrumentation II chapter 2 questions →