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Address decoding for two 8 KB RAM at C000H

Short answer

Each 8KB RAM uses A12–A0. Decoder 74LS138 with C,B,A = A15,A14,A13, G1=+5V, G2B'=GND, G2A'=IO/M'. Y6' selects RAM1 (C000H–DFFFH), Y7' selects RAM2 (E000H–FFFFH). RD' to OE', WR' to WE', A12–A0 to address pins, and D7–D0 connects to data bus.

Draw the address decoding circuit to interface two RAM memory block each of 8 KB at address C000H.

Each 8 KB RAM has 13 address lines (A12–A0). A15, A14, A13 select the chip. The two RAMs occupy consecutive blocks from C000H.

Address map

ChipA15 A14 A13A12–A0Range
RAM 11 1 00…0 to 1…1C000H – DFFFH
RAM 21 1 10…0 to 1…1E000H – FFFFH

Circuit (74LS138)

  • C, B, A = A15, A14, A13. Pattern 110 → Y6' (RAM 1); 111 → Y7' (RAM 2).
  • G1 = +5 V, G2B' = GND, G2A' = IO/M' (decoder active only for memory cycles).
  • Y6' → CS' of RAM 1; Y7' → CS' of RAM 2.
  • A12–A0 → address pins of both RAMs.
  • RD' → OE' and WR' → WE' of both RAMs; D7–D0 are bidirectional and connect to the data bus.
 A15 --- C \
 A14 --- B  | 74LS138      +--------+
 A13 --- A /  Y6' -------- |CS' RAM1| C000-DFFF
 IO/M' - G2A' Y7' ----+    +--------+
 GND --- G2B'         |    +--------+
 +5V --- G1           +----|CS' RAM2| E000-FFFF
                           +--------+
 A12-A0 -> both RAMs   RD'->OE'  WR'->WE'  D7-D0 <-> both

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. Because A15–A13 are fully decoded, RAM 1 responds only to C000H–DFFFH and RAM 2 only to E000H–FFFFH, so there is no address overlap.

✓ Answer checked by Claude Opus 5.5 (high effort)

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