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Interface 4 KB EPROM and two 2 KB RAM

Short answer

EPROM 4K at 0000H–0FFFH, RAM1 2K at 1000H–17FFH, RAM2 2K at 1800H–1FFFH. Decoder: 74LS138 with C,B,A = A13,A12,A11; G1=+5V, G2A'=IO/M', G2B'=A15 OR A14. Y0' and Y1' ANDed drive CE' of EPROM; Y2' and Y3' drive CS' of RAM1 and RAM2. A11–A0 to EPROM, A10–A0 to RAMs, RD' to OE', WR' to WE'.

Design an interfacing circuit to interface one 4 KB EPROM and two 2 KB R/W memory for 8085 microprocessor.

Sizes: 4 KB EPROM = 4096 bytes → 12 address lines (A11–A0). 2 KB RAM = 2048 bytes → 11 address lines (A10–A0).

Memory map

DeviceRangeA15 A14 A13 A12 A11
EPROM 4K0000H – 0FFFH0 0 0 0 x
RAM 1 2K1000H – 17FFH0 0 0 1 0
RAM 2 2K1800H – 1FFFH0 0 0 1 1

The EPROM is placed at 0000H because the 8085 starts at 0000H after reset and needs the start-up program in non-volatile memory.

Decoder circuit (74LS138)

  • C, B, A = A13, A12, A11.
  • EPROM: 000 and 001 → Y0', Y1' joined by an AND gate → CE'.
  • RAM 1: 010 → Y2' → CS'. RAM 2: 011 → Y3' → CS'.
  • G1 = +5 V, G2A' = IO/M', G2B' = A15 OR A14 (both must be 0).
  • RD' → OE' of EPROM and both RAMs; WR' → WE' of both RAMs.
 A13 -- C \
 A12 -- B  | 74LS138
 A11 -- A /   Y0' -+--[AND]--CE' EPROM 4K
 IO/M' - G2A'  Y1' -+         (0000-0FFF)
 A15,A14 -[OR]- G2B'
 +5V ----- G1  Y2' ---------- CS' RAM1 (1000-17FF)
               Y3' ---------- CS' RAM2 (1800-1FFF)
 A11-A0 -> EPROM,  A10-A0 -> RAMs
 RD' -> OE' all,  WR' -> WE' RAMs,  D7-D0 common

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. Only one chip is selected at a time, so the data bus has no conflict.

✓ Answer checked by Claude Opus 5.5 (high effort)

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