- 2073 Magh · 8 marks
74LS138 interfacing of ROM, RAM, EPROM
Short answer
ROM 2K at A000H–A7FFH, RAM 2K at A800H–AFFFH, EPROM 4K at B000H–BFFFH. Decoder: 74LS138 with C,B,A = A13,A12,A11; G1=A15, G2A'=A14, G2B'=IO/M'. Y4' selects ROM, Y5' selects RAM, Y6' and Y7' ANDed select EPROM. RD' to OE' all, WR' to WE' RAM, A10–A0 to 2K chips, A11–A0 to EPROM.
With a neat diagram explain the interfacing circuit using a 3:8 decoder (74LS138) needed to connect the following memory units to the 8085 microprocessor consecutively starting from memory location A000H. 2K×8 ROM chip 2K×8 RAM chip 4K×8 EPROM chip
The decoder must give 2K-block selection, so the select inputs are A13, A12, A11. Chip sizes: 2K×8 needs 11 address lines (A10–A0); 4K×8 needs 12 (A11–A0).
Address map (starting at A000H, consecutive)
| Device | Size | Range | A15 A14 A13 A12 A11 |
|---|---|---|---|
| ROM | 2K | A000H – A7FFH | 1 0 1 0 0 |
| RAM | 2K | A800H – AFFFH | 1 0 1 0 1 |
| EPROM | 4K | B000H – BFFFH | 1 0 1 1 x |
Decoder connections (74LS138)
- C, B, A = A13, A12, A11. ROM: 100 → Y4'. RAM: 101 → Y5'. EPROM: 11x covers 110 and 111 → Y6' and Y7'.
- G1 = A15 (must be 1); G2A' = A14 (must be 0); G2B' = IO/M' (must be 0).
- Y4' → CS' of ROM; Y5' → CS' of RAM.
- Y6' and Y7' are combined by a 2-input AND gate (output low when either is low) → CE' of the 4K EPROM.
- ROM, RAM and EPROM address pins: A10–A0 (2K chips) and A11–A0 (EPROM).
- RD' → OE' of all three; WR' → WE' of the RAM only.
A13 -- C \
A12 -- B | 74LS138 +------+
A11 -- A / Y4' ------- |ROM 2K| A000-A7FF
A15 -- G1 Y5' ------- |RAM 2K| A800-AFFF
A14 -- G2A' +------+
IO/M' - G2B'
Y6' --+
[AND]---- |EPROM 4K| B000-BFFF
Y7' --+
A10-A0 -> ROM, RAM; A11-A0 -> EPROM
RD' -> OE' (all); WR' -> WE' (RAM); D7-D0 common
The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. Only one chip select is low at a time, so only one device drives the data bus.
✓ Answer checked by Claude Opus 5.5 (high effort)
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