DMA concept; ROM/RAM interface at 4000H

Concept of DMA

In DMA a DMA controller (8237) moves data between an I/O device and memory directly, without CPU instructions for each byte. The device asks with DREQ, the controller sends HOLD, the CPU gives the bus and answers HLDA, then the controller sends the address and MEMR'/MEMW', IOR'/IOW' signals and transfers bytes at high speed. It is used for block transfers like ADC data capture.

Memory interface (8085, base address 4000H)

• 4 KB ROM needs 12 address lines (A0-A11): ROM = 4000H-4FFFH.
• 8 KB RAM needs 13 address lines (A0-A12) and must start at a multiple of 2000H, so RAM = 6000H-7FFFH (5000H-5FFFH is unused).

Decoder: 74LS138 with inputs C=A15, B=A14, A=A13, enables G1=1 (or IO/M' via G2B'), G2A'=0. Output Y2 (010) selects 4000H-5FFFH; Y3 (011) selects 6000H-7FFFH.

 8085
 A0-A11  ------------------> ROM 4Kx8 (A0-A11)
 A0-A12  ------------------> RAM 8Kx8 (A0-A12)
 AD0-AD7 (via 74LS373 for low address; direct for data) ---> D0-D7
 A15,A14,A13 -> [74LS138] Y2 --+
 A12 ----------------------> [OR] --> ROM CS'
                    Y3 -------------> RAM CS'
 RD'  -> ROM OE', RAM OE'   WR' -> RAM WE'
 IO/M' -> G2B' (enable decoder only for memory cycles)

ALE with a 74LS373 latch separates A0-A7 from AD0-AD7.

Timing diagrams (8085 memory cycle, 3 T-states)

        T1      T2      T3
CLK   _|-|_|-|_|-|_|-|_|-|_
ALE    __|--|______________
AD0-7 --< A0-A7 >< DATA >--     READ
A8-15 -----< address >-----
RD'   -------\________/----

        T1      T2      T3
ALE    __|--|______________
AD0-7 --< A0-A7 >< DATA out>    WRITE
A8-15 -----< address >-----
WR'   -------\________/----

In a read cycle the address is placed on the bus in T1, RD' goes low in T2 and the memory puts data on the bus, which the CPU latches at the rising edge of RD'. In a write cycle the CPU places data on AD0-AD7 and WR' low writes it into the RAM.