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8255 mode 2 operation with timing diagram

Short answer

Mode 2 is the bidirectional bus mode for port A only, using PC3–PC7 for handshaking (OBF_A', ACK_A', IBF_A, STB_A', INTR_A). Control word C0H configures port A in mode 2 with port B mode 0 output; BSR 0DH and 09H enable output and input interrupts. Data output uses WR' and ACK_A'; input uses STB_A' and RD'.

With a neat timing diagram and an appropriate example, explain the operation of 8255 PPI in mode 2. You should clearly show the necessary control signals and an interfacing circuit to connect 8255PPI to 8085 microprocessor. Also write the necessary control words to configure the 8255 in this fashion.

Mode 2 is the bidirectional bus mode of the 8255. It is available only for port A (8 lines PA0-PA7). The same eight lines are used for both input and output, and five lines of port C (PC3-PC7) are used for handshaking. Port B can be in mode 0 or mode 1.

Control signals (port A, mode 2)

PinSignalMeaning
PC7OBF_A'Output buffer full: CPU wrote data, peripheral may read
PC6ACK_A'Peripheral acknowledge: enables the output buffer onto PA0-PA7
PC5IBF_AInput buffer full: data latched from peripheral
PC4STB_A'Strobe from peripheral to load the input latch
PC3INTR_AInterrupt request to CPU for both input and output

INTE1 (PC6 bit set) enables the output interrupt, and INTE2 (PC4 bit set) enables the input interrupt.

Operation and timing

Output: the CPU writes data to port A. The rising edge of WR' makes OBF_A' low (data ready). The peripheral pulls ACK_A' low; this opens the output buffer so the data appear on PA0-PA7, and OBF_A' goes high again. When ACK_A' returns high, INTR_A is set (if INTE1 = 1). The next falling edge of WR' clears it.

Input: the peripheral sends data with STB_A' low; the data are latched and IBF_A goes high. When STB_A' returns high, INTR_A goes high (if INTE2 = 1). The CPU then reads port A: INTR_A goes low when RD' falls and IBF_A goes low when RD' rises.

Output timing (Z = high impedance):

 WR'   ----\__/------------------------
 OBF'  --------\_________/-------------
 ACK'  ------------------\____/--------
 PA    ZZZZZZZZZZZZZZZZZZ<data>ZZZZZZZZ
 INTR  _______________________/--------

Input timing:

 PA    --< data from peripheral >------
 STB'  -----\____/---------------------
 IBF   _____/----------------\_________
 INTR  __________/------\______________
 RD'   -----------------\____/---------

Interfacing circuit with 8085 (I/O mapped, ports 80H-83H)

 8085 AD0-AD7 -> 74LS373 -> A0,A1 -> 8255 A0,A1
 AD0-AD7 ----> D0-D7 of 8255 (via data lines)
 A7=1, A6-A2=0 decoder -> CS' ;  IOR' -> RD' ;  IOW' -> WR'
 RESET OUT -> RESET
 PA0-PA7 <-> peripheral data bus
 PC7 OBF', PC6 ACK', PC5 IBF, PC4 STB' <-> peripheral
 PC3 INTR_A -> RST 5.5 / INTR of 8085

Control word (mode 2, port B mode 0 output)

D7 = 1, D6 D5 = 1 x (mode 2), D4 = x, D3 = x, D2 = 0 (B mode 0), D1 = 0 (B output), D0 = x. With x = 0: 1100 0000 = C0H. If port B is mode 1 output: 1100 0100 = C4H. To enable the interrupts: BSR 0DH (set PC6, INTE1) and 09H (set PC4, INTE2).

Example

Data transfer between two microcomputers over a common 8-bit bus, or to a floppy disk controller, where the CPU sends commands and receives data through the same eight lines.

✓ Answer checked by Claude Sonnet 5.5

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