Skip to main content

Double handshake data transfer with 8255-PPI

Short answer

8255 port A mode 1 input: STB' (PC4) latches data, IBF (PC5) goes high, INTR (PC3) interrupts CPU. Control word B0H, INTE set by BSR 09H. Base address 80H, control register 83H.

Consider a double handshake scheme that allows data transfer from an input peripheral device to an 8085-microprocessor through an 8255-PPI. (i) List all control signals that get exchanged between the devices. (ii) Draw a detailed timing diagram showing the exchange of control and data signals. Include the cause and effect arrows in your timing diagram. (iii) With a neat sketch show the overall system diagram between the modules mentioned above. (iv) Generate an appropriate control word based upon your drawing and derive the address of the control register of the 8255-PPI used in your design.

In the double handshake method, each data transfer needs two signals in each direction: the peripheral says "data is ready" and the interface says "data was received". We use the 8255 port A in mode 1 (strobed input).

(i) Control signals

  • From the peripheral: STB' (strobe, data valid), 8-bit data on PA0-PA7.
  • From the 8255: IBF (input buffer full, acknowledge to the peripheral), INTR (interrupt request to 8085, PC3), controlled by INTE.
  • From the 8085: RD', CS', A0, A1 and RESET.

(ii) Timing diagram with cause and effect

 Data  ---< valid >----------------------------
 STB'  -----\_______/--------------------------
 IBF   ____________/----------------\_________
 INTR  ________________/-----------\__________
 RD'   ---------------------\____/-------------
 (1) STB' low -> data latched
 (2) STB' low -> IBF high (peripheral told: wait)
 (3) STB' rising (and INTE=1) -> INTR high
 (4) 8085 ISR: RD' low -> INTR low
 (5) RD' rising -> IBF low (peripheral can send next byte)

(iii) System diagram

 Peripheral              8255               8085
 D0-D7 ------------> PA0-PA7  D0-D7 <----> AD0-AD7
 STB'  ------------> PC4                  RD',WR'
 IBF   <------------ PC5      CS',A0,A1 <- decoder, A0,A1
                      PC3 INTR ---------> RST 5.5 (INTR input)

(iv) Control word and address

Assume I/O mapped 8255 with base address 80H (A7 = 1 selects it, A1A0 select register): Port A = 80H, B = 81H, C = 82H, control = 83H. Control word: D7=1; D6D5 = 01 (port A mode 1); D4 = 1 (A input); D3 = 0 (PC6, PC7 output); D2 = 0 (port B mode 0); D1 = 0 (B output); D0 = 0 (C lower output) = 1011 0000 = B0H. Enable INTE_A by BSR of PC4: control word 0000 1001 = 09H.

        MVI A,B0H
        OUT 83H
        MVI A,09H
        OUT 83H     ; INTE A = 1
        EI

The ISR executes IN 80H to get the data.

✓ Answer checked by Claude Sonnet 5.5

Related questions

All Instrumentation II chapter 2 questions →