Why can the 8085 address 64 KB of memory but only 256 I/O ports?

Memory addresses are 16 bits (2^16 = 64K) while I/O port addresses are 8 bits (2^8 = 256)

Memory uses a 20-bit address while I/O uses a 16-bit address

The data bus is 8 bits, which limits memory to 64 KB

I/O ports share the multiplexed AD0-AD7 lines, so only half the addresses are available

What is the purpose of the ALE signal in the 8085?

It goes high in T1 so an external latch (such as 74LS373) can save the low-order address A7-A0 from the multiplexed AD7-AD0 lines

It enables the higher-order address lines A15-A8

It tells memory to put data on the bus during a read

It acknowledges that the bus has been released to a DMA controller

Which statement about the 8085 interrupts is correct?

TRAP is non-maskable, and INTR is non-vectored (the interrupting device supplies the instruction)

All five interrupts are maskable and vectored

INTR is non-maskable, and TRAP is non-vectored

RST7.5 is non-maskable because it has the highest priority among RST interrupts

2073 Bhadra · 2+6 marks

Characteristics and signals of 8085

Short answer

The 8085 is an 8-bit NMOS microprocessor with 64 KB address space, 256 I/O ports, +5 V supply, on-chip clock, five interrupts, and DMA support. Output signals include A15-A8, AD7-AD0, ALE, RD, WR, IO/M, S1/S0, INTA, HLDA, CLK OUT, RESET OUT, and SOD.

What are the characteristics of 8085 microprocessor? Discuss all the input and output signals that are originated from microprocessor.

Characteristics of the 8085

8-bit microprocessor, NMOS technology, 40-pin DIP.
8-bit data bus and 16-bit address bus: 64 KB memory; 256 I/O ports (8-bit port address).
Single +5 V supply; on-chip clock generator and oscillator (3 MHz max).
Multiplexed lower address/data bus (AD0-AD7) using ALE.
Five interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR. All are maskable except TRAP; all are vectored except INTR (the interrupting device supplies the instruction).
Serial I/O using SID and SOD; DMA support with HOLD and HLDA.
74 instructions (246 opcodes); general registers B, C, D, E, H, L; 16-bit SP and PC.

Signals generated (output) by the 8085

Signal	Description
A15-A8	Higher-order address lines, unidirectional, output.
AD7-AD0	Multiplexed low-order address and data (bidirectional); address in T1, data after.
ALE	Address Latch Enable; high in T1 so an external latch (74LS373) can save A7-A0.
RD	Active-low read control; the selected memory/I/O puts data on the data bus.
WR	Active-low write control; data on the bus is to be written.
IO/M	High for I/O operation, low for memory operation.
S1, S0	Status; with IO/M define the machine cycle (00 halt, 01 write, 10 read, 11 fetch).
INTA	Interrupt acknowledge, tells the interrupting device the CPU accepted INTR.
HLDA	Hold acknowledge, confirms bus is released to DMA controller.
CLK (OUT)	System clock output for other devices.
RESET OUT	Indicates CPU is being reset; used to reset peripherals.
SOD	Serial output data.

(Input signals are HOLD, READY, INTR, TRAP, RST7.5/6.5/5.5, SID, RESET IN, X1, X2.)

✓ Answer checked by Claude Opus 5.5 (high effort)

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Characteristics and signals of 8085

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