Internal architecture of 8085

The 8085 is an 8-bit microprocessor with a 16-bit address bus, made in NMOS technology, single +5 V supply, 3 MHz (max) clock. Its internal architecture has the following blocks.

 +--------------------------------------------------+
 | Interrupt control |  Serial I/O control          |
 | INTR INTA RST TRAP|     SID       SOD            |
 +--------------------------------------------------+
 | Accum.(A) |Temp reg|  W  | Z |  B  | C |  D | E  |
 | Flags     |        |         |  H  | L |  SP | PC |
 |    \_____ ALU _____/         |   Inc/Dec address  |
 |                              |   latch            |
 +--------------------------------------------------+
 | Instruction reg -> Decoder -> Timing and control |
 |                      ALE RD WR IO/M S0 S1 READY  |
 +--------------------------------------------------+
 | Addr buffer (A15-A8) |  Addr/Data buffer (AD7-0) |
 +--------------------------------------------------+
         8-bit internal data bus runs through all

1. ALU

Performs arithmetic (add, subtract, increment, decrement) and logic (AND, OR, XOR, compare, rotate, complement) operations. One input comes from the accumulator and the other from the temporary register. The result goes back to the accumulator.

2. Accumulator (A) and temporary register

The 8-bit accumulator holds one operand and the result. The temporary register is invisible to the programmer and holds the second operand during the ALU operation.

3. Flag register

Five flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry (CY). They show the status of the last arithmetic/logic result.

4. General purpose registers

B, C, D, E, H, L (8-bit each); they work singly or as BC, DE, HL pairs. W and Z are temporary registers used internally by CALL, XCHG etc.; they are not available to the programmer.

5. Program Counter (PC) and Stack Pointer (SP)

Both are 16-bit. PC holds the address of the next instruction to be fetched. SP holds the address of the top of the stack in memory.

6. Increment/Decrement address latch

Increments or decrements PC/SP (or register pair) after every fetch, push and pop.

7. Instruction register and decoder

The opcode fetched is stored in the instruction register (IR) and decoded by the instruction decoder.

8. Timing and control unit

Generates timing and control signals (ALE, RD, WR, IO/M, S0, S1) and synchronises all operations using the clock from the on-chip clock generator.

9. Interrupt control

Handles TRAP, RST7.5, RST6.5, RST5.5, INTR and sends INTA.

10. Serial I/O control

Handles serial data in (SID) and serial data out (SOD) using the RIM and SIM instructions.

11. Address buffer and address/data buffer

The address buffer drives the higher-order address A15-A8. The address/data buffer drives the multiplexed lines AD7-AD0 (low-order address and data), separated using ALE.