DMA controller block diagram and transfer

A DMA (direct memory access) controller transfers blocks of data between an I/O device and main memory without passing each word through the CPU.

Block diagram

        Address bus <----> +--------------------+
   (from CPU)  DS --------> | Address register   |
               RS --------> +--------------------+
               RD  <------> | Word count register|
               WR  <------> +--------------------+
   Data bus <------------> | Control register   |
                            +--------------------+
                            |  Control logic     |
   BR  (bus request)  <-----|                    |
   BG  (bus grant)    ----->|                    |
   Interrupt          <-----|                    |
   DMA request  <-----------|  from I/O device   |
   DMA acknowledge ---------->  to I/O device    |
                            +--------------------+

• Address register: holds the memory address of the next word to transfer; it increments after each word.
• Word count register: holds the number of words left; it decrements after each word. When it reaches zero the transfer is finished and an interrupt is sent to the CPU.
• Control register: sets the mode of transfer (read or write, burst or cycle stealing).
• DS, RS (DMA select, register select): the CPU uses them with RD/WR to program the three registers through the data bus.
• BR, BG: the DMA controller asks the CPU for the buses with BR; the CPU grants them with BG and tri-states its address, data and control lines.
• DMA request / acknowledge: handshake lines with the I/O device.

Data transfer from a peripheral using DMA

1. Initialisation by CPU: the CPU writes the starting memory address, the word count and the transfer direction into the DMA controller, and starts the device. The CPU then continues with other work.
2. DMA request: when the peripheral has data ready, it sends a DMA request to the controller.
3. Bus request: the controller sends BR to the CPU.
4. Bus grant: the CPU finishes its current bus cycle, floats its buses and replies with BG.
5. Acknowledge: the controller sends DMA acknowledge to the device and places the address register on the address bus.
6. Transfer: one word moves directly between the device and memory (write or read signal from the controller). The address register is incremented and the word count is decremented.
7. Repeat or release: in burst mode the controller keeps the bus until the block is done; in cycle-stealing mode it releases the bus after every word.
8. Completion: when the word count becomes zero, the controller drops BR and interrupts the CPU. The CPU then takes back control and checks the status.