DMA controller and flow of actions

Purpose of the DMA controller

A direct memory access (DMA) controller transfers blocks of data directly between a peripheral and memory without the processor handling each byte. The processor only sets up the transfer (starting address, number of bytes, direction); the DMA controller then takes the bus and performs the transfers itself. This frees the CPU for other work, gives much higher transfer rates than interrupt-driven or polled I/O, and avoids the overhead of ISR entry/exit for each word.

Block diagram

 +-----------+  Hold/Req  +-------------+   Req/Ack  +------------+
 | Processor |<---------->|  DMA        |<---------->| Peripheral |
 |           |  Hlda/Ack  | controller  |            +-----+------+
 +-----+-----+            | (address    |                  |
       |                  |  reg, count |                  |
       |                  |  reg, ctrl) |                  |
       |                  +------+------+                  |
 ======+==================== Address / Data / Control bus ==+====
                                |
                           +----+-----+
                           |  Memory  |
                           +----------+

Flow of actions (peripheral to memory)

1. The processor is running its main program and sets up the DMA controller registers: starting memory address, byte count and direction (e.g. 100 for the address, 4 bytes), then continues its work.
2. The peripheral has data and asserts Req (DMA request) to the DMA controller.
3. The DMA controller asserts Hold/Bus request to the processor.
4. The processor finishes its current bus cycle, releases the address/data/control buses and sends Hlda/Ack (bus granted).
5. The DMA controller sends Ack to the peripheral and places the memory address on the address bus.
6. The peripheral places the data on the data bus; memory is written (M[address] = data) in one bus cycle.
7. The DMA controller increments the address and decrements the count. Steps 2 to 6 repeat until the count is zero.
8. The DMA controller releases the bus (drops Hold) and raises an interrupt to inform the processor that the transfer is complete; the processor resumes use of the bus.