Skip to main content

Cache memory mapping techniques

Short answer

Cache memory provides fast storage for frequently accessed data. Mapping techniques: direct (fixed line by index), fully associative (any line, tag compared in parallel), set-associative (block to a set, placed in any way). Direct mapping is simple and cheap but has conflict misses; fully associative gives highest hit rate with costly parallel comparators.

What is cache memory? What are the basic techniques for cache mapping? How do direct mapping and fully associative mapping differ?

Cache memory is a small, fast memory placed between the processor and the main memory that holds copies of frequently used data/instructions, using the principle of locality. A hit gives data in one cache access; a miss goes to main memory. Because the cache is much smaller than main memory, a rule is needed to decide where each memory block may be placed. This rule is the mapping technique.

Memory address splits into tag | index | offset. The offset selects the byte within a block, the index selects the cache line or set, and the tag identifies which memory block is stored there.

Basic mapping techniques

  1. Direct mapping: each main-memory block can go into exactly one cache line: line = (block address) mod (number of lines).
  2. Fully associative mapping: a block can be placed in any cache line. The tag is the whole block address, compared with all line tags in parallel.
  3. Set-associative mapping: the cache is divided into sets. A block maps to one set and can be in any line (way) of that set, e.g. 2-way or 4-way.
 Direct:  address = | tag | index | offset |
          index -> one line -> compare 1 tag
 Assoc.:  address = | tag (block no.) | offset |
          compare tag with ALL lines at once

Direct versus fully associative mapping

PointDirect mappingFully associative
PlacementOnly one possible lineAny line
Address fieldstag, index, offsettag, offset (no index)
Comparators1One per line (all in parallel)
Hardware costLow, simpleHigh, expensive (CAM)
Hit timeFastSlower, more complex search
Conflict missesHigh (two hot blocks may fight for one line)None (only capacity misses)
Replacement policyNot neededNeeded (LRU, FIFO, random)
Hit ratioLowerHighest
UseLarge cachesSmall caches, TLBs

✓ Answer checked by Claude Opus 5.5 (high effort)

All Embedded System chapter 4 questions →