Need for IOP and DMA control

Need for an I/O processor

An input-output processor (IOP) is a processor with its own instruction set and control unit that handles all I/O transfers, so the CPU is free for computation. It is needed because:

• With programmed or interrupt-driven I/O, the CPU is busy during every transfer or interrupt, and the system slows down when there are many devices.
• A single DMA controller handles only simple block transfers. An IOP can do more: format conversion, error checking, code conversion, and chained transfers described by an I/O program.
• Devices differ in speed, word format and control. The IOP hides these differences and gives the CPU one simple interface.
• The IOP works in parallel with the CPU, so overall throughput and CPU utilisation rise.
• Many peripherals can be attached to one IOP (a channel), which reduces the load on the CPU and the system bus.

        +---------+          +-------------------+
        | Memory  |<-------->|   Memory bus      |
        |  unit   |          +----+---------+----+
        +---------+               |         |
                              +---v---+  +--v----+
                              |  CPU  |  |  IOP  |
                              +-------+  +--+----+
                                            | I/O bus
                          +---------+-------+---------+
                          v         v                 v
                      Keyboard    Printer           Disk
                                  (peripherals)

DMA control

DMA control lets an I/O device transfer data directly to or from memory without the CPU handling every word. The DMA controller has an address register, a word count register and a control register, with BR/BG lines for the bus.

                          +---------------------+
   Address bus  <-------->| Address register    |
   Data bus     <-------->| Word count register |
                          | Control register    |
                          +---------------------+
   DS (DMA select) ------>|                     |
   RS (reg. select) ----->|                     |
   RD (read)    <-------->|    Control logic    |
   WR (write)   <-------->|                     |<---- DMA request (from I/O device)
   BR (bus request) <-----|                     |----> DMA acknowledge (to I/O device)
   BG (bus grant) ------->|                     |
   Interrupt    <---------|                     |
                          +---------------------+

• Address register: holds the memory address of the next word to transfer; it increments after each word.
• Word count register: holds the number of words left; it decrements after each word. When it reaches zero, the transfer is finished and an interrupt is sent to the CPU.
• Control register: sets the mode of transfer (read or write, burst or cycle stealing).
• DS, RS (DMA select, register select): the CPU uses them with RD/WR to program the three registers through the data bus.
• BR, BG: the DMA controller asks the CPU for the buses with BR; the CPU grants them with BG and puts its address, data and control lines in the high-impedance state.
• DMA request / acknowledge: handshake lines with the I/O device.

Steps in a DMA transfer

1. Initialisation by CPU: the CPU writes the starting memory address, the word count and the transfer direction into the DMA controller, and starts the device. The CPU then continues with other work.
2. DMA request: when the peripheral has data ready, it sends a DMA request to the controller.
3. Bus request: the controller sends BR to the CPU.
4. Bus grant: the CPU finishes its current bus cycle, floats its buses and replies with BG.
5. Acknowledge: the controller sends DMA acknowledge to the device and places the contents of the address register on the address bus.
6. Transfer: one word moves directly between the device and memory (the controller drives the read or write signal). The address register is incremented and the word count is decremented.
7. Repeat or release: in burst mode, the controller keeps the bus until the whole block is done; in cycle-stealing mode, it releases the bus after every word.
8. Completion: when the word count becomes zero, the controller drops BR and interrupts the CPU. The CPU then takes back control and checks the status.