Microprogram control unit organization

A microprogrammed control unit generates control signals by reading microinstructions from a control memory, instead of using fixed logic. Each machine instruction is carried out by a sequence of microinstructions (a microprogram or routine).

 Instruction register (opcode)
          |
   +------v------+   +----------------+
   | Mapping     |-->|     CAR        |<-- next-address
   | logic       |   | (control addr) |    generator
   +-------------+   +-------+--------+    (sequencer)
                             |                  ^
                     +-------v--------+         |
                     |  Control memory|         | status,
                     |   (ROM)        |         | branch fields
                     +-------+--------+         |
                     +-------v--------+---------+
                     | Control data   |
                     | register (CDR) |
                     +-------+--------+
                             v
                  control signals to ALU, registers, buses

Components

• Control memory (ROM): stores the microprograms permanently. For Mano's computer it is 128 × 20 bits.
• Control address register (CAR): holds the address of the next microinstruction.
• Sequencer (next-address logic): selects CAR + 1, the branch address, the return address (from SBR) or the mapped address.
• Control data register (pipeline register): holds the microinstruction being executed, so that the next one can be fetched while it executes.
• Mapping logic: converts the opcode of the machine instruction to the starting address of its routine.
• Subroutine register (SBR): stores the return address for micro-subroutines.

Generation of control signals

1. The fetch routine is the first microprogram to run (CAR = 64). It loads the instruction into IR.
2. The opcode is mapped to the address of the routine for that instruction, and this address is loaded into CAR.
3. The microinstruction read from the control memory goes to the CDR. Its microoperation fields F1, F2, F3 are decoded by 3-to-8 decoders; each decoder output is a control signal (for example PCTAR, READ, INCPC) that enables a datapath transfer.
4. The CD, BR and AD fields go to the sequencer, which decides the next address.
5. At the end of the routine, a branch goes back to FETCH, and the cycle repeats.