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Control signal types and hardware control unit

Short answer

Control signals activate ALU functions, data path transfers, or system bus operations. Hardware implementation lists microoperations per timing step, derives Boolean expressions for each control signal as OR of (timing AND instruction AND flags), generates timing from a counter/decoder, decodes the opcode, and implements the expressions with gates.

What are the three types of control signals? Explain the key steps of hardware implementation of the control unit.

Three types of control signals

  1. Signals that activate an ALU function (add, subtract, AND, shift).
  2. Signals that activate a data path: open the gates that connect registers to buses or to the ALU (for example C1: MAR ← PC; C2: MBR ← memory).
  3. Signals on the external system bus or interface: memory read, memory write, I/O read, I/O write, interrupt acknowledge.

Hardware (hardwired) implementation of the control unit

A hardwired control unit produces each control signal with a logic circuit that depends on the instruction, the timing and the flags.

 Clock --> [Counter] --> [Timing decoder] --T1,T2,T3..-+
                                                        v
 IR --> [Instruction decoder] --I1,I2..--> [ Control   ]--> control
 Flags (status) ----------------------------> [ logic   ]    signals
 Control bus signals (interrupts etc.) ------>[ gates   ]

Key steps:

  1. List the microoperations of the fetch, indirect, execute and interrupt cycles, and place them in time steps (T1, T2, T3, ...). Example fetch: T1: MAR ← PC; T2: MBR ← M[MAR], PC ← PC + 1; T3: IR ← MBR.
  2. Find the control signals needed for each microoperation (gate enables, ALU function selects, memory read/write).
  3. Write a Boolean expression for each control signal as the OR of all conditions (timing AND instruction AND flag) under which it must be 1. For example, if the memory read signal C5 is needed at T2 of fetch and at T2 of the execute cycle of LOAD and ADD: C5 = P1·T2 + P2·T2·(I_LOAD + I_ADD), where P1, P2 are cycle indicators.
  4. Generate the timing signals with a clock, a counter and a decoder (T1..Tn), which restarts at the end of each instruction.
  5. Decode the opcode in IR with a decoder to give a separate line I_k for each instruction.
  6. Implement the expressions with gates (AND/OR) fed by the timing, instruction, flag and bus signals. The outputs are the control signals sent to the datapath, ALU and system bus.
  7. Reset the counter at the end of the instruction cycle and handle the interrupt check.

✓ Answer checked by Claude Opus 5.5 (high effort)

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