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Microinstruction format and fetch microprogram
Short answer
The format uses three 3-bit fields (F1, F2, F3) for microoperations, a 2-bit CD condition, a 2-bit BR branch type, and a 7-bit AD. The fetch routine at address 64 does: PCTAR; then READ,INCPC; then DRTAR with MAP to branch to the execute routine of the fetched instruction.
Explain the microinstruction format used in a microprogrammed control unit and write the micro program for the fetch cycle.
A microprogrammed control unit stores in its control memory a microprogram for each instruction. Each microinstruction has fields which select microoperations and the address of the next microinstruction.
Microinstruction format (Mano, 20 bits)
| F1 | F2 | F3 | CD | BR | AD |
| 3 | 3 | 3 | 2 | 2 | 7 | = 20 bits
| Field | Bits | Meaning |
|---|---|---|
| F1, F2, F3 | 3 each | Three microoperation fields. Each selects one of 7 microoperations (000 = none), so up to 3 can be done at the same time. |
| CD | 2 | Condition: 00 = U (always 1), 01 = I (indirect bit DR(15)), 10 = S (sign of AC), 11 = Z (AC is zero) |
| BR | 2 | Branch type: 00 JMP, 01 CALL, 10 RET, 11 MAP |
| AD | 7 | Address of the next microinstruction when branching (control memory of 128 words) |
Microoperation codes:
| F1 | Operation | F2 | Operation | F3 | Operation |
|---|---|---|---|---|---|
| 001 | AC ← AC + DR | 001 | AC ← AC - DR | 001 | AC ← AC xor DR |
| 010 | AC ← 0 | 010 | AC ← AC or DR | 010 | AC ← AC' |
| 011 | AC ← AC + 1 | 011 | AC ← AC and DR | 011 | shl AC |
| 100 | AC ← DR | 100 | DR ← M[AR] | 100 | shr AC |
| 101 | AR ← DR(0-10) | 101 | DR ← AC | 101 | PC ← PC + 1 |
| 110 | AR ← PC | 110 | DR ← DR + 1 | 110 | PC ← AR |
| 111 | M[AR] ← DR | 111 | DR(0-10) ← PC | 111 | not used |
The fields can be written symbolically, for example READ, INCPC U JMP NEXT, which uses F2 and F3 with an unconditional jump to the next address.
Fetch cycle microprogram
The fetch cycle needs these register transfers: AR ← PC; DR ← M[AR], PC ← PC + 1; AR ← DR(0–10), then branch to the routine of the opcode (MAP). The fetch routine starts at address 64 of the control memory.
| Address (dec / bin) | Label | Microoperations | CD | BR | AD | Binary F1 F2 F3 CD BR AD |
|---|---|---|---|---|---|---|
| 64 / 1000000 | FETCH | PCTAR | U | JMP | NEXT | 110 000 000 00 00 1000001 |
| 65 / 1000001 | - | READ,INCPC | U | JMP | NEXT | 000 100 101 00 00 1000010 |
| 66 / 1000010 | - | DRTAR | U | MAP | 0 | 101 000 000 00 11 0000000 |
Symbolic form:
ORG 64
FETCH: PCTAR U JMP NEXT ; AR <- PC
READ, INCPC U JMP NEXT ; DR <- M[AR], PC <- PC + 1
DRTAR U MAP ; AR <- DR(0-10), go to routine
The MAP microinstruction takes the opcode from DR and maps it to the start address of the execute routine (0 xxxx 00, so ADD = 0, BRANCH = 4, STORE = 8, EXCHANGE = 12).
✓ Answer checked by Claude Opus 5.5 (high effort)
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