Microinstruction format and microprogram design

Microinstruction format

Use Mano's 20-bit format with a 128-word control memory (7-bit address).

 | F1(3) | F2(3) | F3(3) | CD(2) | BR(2) | AD(7) |

• F1, F2, F3: microoperation fields. F1: 001 ADD (AC←AC+DR), 100 DRTAC, 101 DRTAR (AR←DR(0-10)), 110 PCTAR (AR←PC), 111 WRITE. F2: 100 READ (DR←M[AR]), 101 ACTDR, 111 PCTDR. F3: 101 INCPC (PC←PC+1), 110 ARTPC.
• CD: 00 U (always true), 01 I (indirect bit DR(15)), 10 S (sign of AC), 11 Z (zero of AC).
• BR: 00 JMP, 01 CALL, 10 RET, 11 MAP.
• AD: branch address.

Memory layout

Fetch routine at 64, indirect routine at 67, ADD routine at 0 (opcode 0000 maps to 0 0000 00 = 0).

Symbolic microprogram

        ORG 0
ADD:    NOP              I  CALL  INDRCT   ; if I = 1, do indirect
        READ             U  JMP   NEXT     ; DR <- M[AR]
        ADD              U  JMP   FETCH    ; AC <- AC + DR, go to fetch
        ORG 64
FETCH:  PCTAR            U  JMP   NEXT     ; AR <- PC
        READ, INCPC      U  JMP   NEXT     ; DR <- M[AR], PC <- PC + 1
        DRTAR            U  MAP            ; AR <- DR(0-10), map opcode
INDRCT: READ             U  JMP   NEXT     ; DR <- M[AR]
        DRTAR            U  RET            ; AR <- DR(0-10), return

Binary microprogram

(The AD field of MAP and RET is not used and is 0000000; the fetch routine ends with MAP so the opcode of DR chooses the next routine.)

Sequencing technique

The sequencer selects the next control address (CAR) from four sources:

• CAR + 1 when BR = JMP and the condition is false (or for sequential microinstructions),
• AD field when BR = JMP or CALL and the condition (CD) is true,
• SBR when BR = RET (return address saved by CALL),
• mapping logic (0 + opcode + 00) when BR = MAP.

 opcode -> map -+
 AD field ------+--> MUX --> CAR --> Control memory
 SBR -----------+     ^
 CAR+1 ---------------+  (select by CD, BR via branch logic)

Execution of ADD: fetch (64–66) loads AR and maps to address 0. At 0, if I = 1 (indirect) CALL INDRCT (67) saves return address 1 in SBR; INDRCT reads the effective address and RET goes back to address 1. At 1, DR ← M[AR]; at 2, AC ← AC + DR and the jump to FETCH starts the next instruction.