Fetch and execution cycle with RTL

In a stored program computer, every instruction goes through a fetch cycle (bring the instruction from memory to the CPU) and an execute cycle (do what the instruction says). Registers used: PC (address of next instruction), MAR (memory address register), MDR/MBR (data read or to be written), IR (instruction register), AC/A (accumulator), and W, Z (temporary registers that hold a 16-bit address, WZ, for LDA and JMP). The steps below are general register transfers (t1, t2, … are micro-steps, not 8085 T-states; on the 8085, LDA takes 4 machine cycles and 13 T-states).

Fetch cycle

The control unit does the following in the first clock periods:

t1: MAR <- PC          ; address of instruction to address bus
t2: MDR <- M[MAR]      ; memory read, instruction comes to MDR
    PC  <- PC + 1      ; point to next instruction
t3: IR  <- MDR         ; instruction goes to IR
t4: decode IR          ; control unit decodes opcode

Execute cycle

The steps depend on the instruction. Examples:

1. ADD B (register operand, A <- A + B)

t5: TEMP <- B          ; B goes to the ALU's temporary register
t6: A <- A + TEMP ; update flags

2. LDA addr (direct memory operand, A <- M[addr])

t5: MAR <- PC ; fetch low address byte
t6: MDR <- M[MAR] ; PC <- PC + 1 ; Z <- MDR
t7: MAR <- PC ; fetch high address byte
t8: MDR <- M[MAR] ; PC <- PC + 1 ; W <- MDR
t9: MAR <- WZ
t10: MDR <- M[MAR]
t11: A <- MDR

3. JMP addr

t5-t8: read address bytes into W and Z
t9: PC <- WZ

 +-------+     +--------+     +---------+
 | Fetch |---->| Decode |---->| Execute |--+
 +-------+     +--------+     +---------+  |
     ^                                      |
     +--------------------------------------+

After execution, the CPU returns to the fetch cycle for the next instruction. RTL makes every step a precise register transfer, which the control unit turns into control signals.