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Stored program concept and processing cycle

Short answer

In a stored program computer, instructions and data reside in the same read/write memory, so any program can run by changing memory contents. The processing cycle repeatedly fetches the instruction (PC→MAR, IR←M[PC], PC+1), decodes the opcode, fetches operands if needed, executes the operation, stores results, and checks for interrupts.

What do you mean by the stored program concept? Explain the processing (instruction) cycle of a stored program (Von Neumann) computer.

The stored program concept (Von Neumann architecture) means that both the program (instructions) and the data are stored together in the same read/write memory, as binary numbers. The CPU fetches instructions from memory one by one and executes them in sequence, so changing the program only needs new contents in memory, not new wiring.

Main features

  • One memory holds instructions and data; each location has an address.
  • A Program Counter (PC) holds the address of the next instruction, so execution is sequential unless a jump/call changes the PC.
  • Instructions are fetched, decoded and executed by the control unit and ALU.
  • The same memory can be loaded with any program, so one machine does many tasks.
 +-----+  address  +---------------+
 | CPU |---------->| MEMORY        |
 | CU  |<--------->| program + data|
 | ALU |   data    +---------------+
 +-----+

Processing (instruction) cycle

The CPU repeats the following cycle for every instruction.

  1. Fetch: the address in PC is sent to memory, the instruction byte is read, placed in the Instruction Register (IR), and PC is incremented to point to the next byte.
  2. Decode: the control unit decodes the opcode in IR and finds out the operation and how many more bytes (operands) are needed.
  3. Fetch operand (if needed): extra bytes or data from memory/registers are read.
  4. Execute: the ALU or other unit performs the operation (add, move, jump, etc.).
  5. Store result (the end of the execute phase): the result is written to a register or memory, and flags are updated.
  6. Check for interrupts: before the next fetch, the CPU checks for a pending interrupt; if one is accepted, an interrupt cycle runs instead of the next fetch. Otherwise the cycle repeats from step 1.

In RTL form:

Fetch:   MAR <- PC
         MDR <- M[MAR]
         PC  <- PC + 1
         IR  <- MDR
Decode:  control unit decodes IR
Execute: operation specified by the opcode,
         e.g. ADD r:  A <- A + r ; update flags

The cycle stops when a halt instruction is executed or power is removed.

✓ Answer checked by Claude Opus 5.5 (high effort)

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