Instruction cycle state diagram with interrupt

The instruction cycle is the sequence of steps the CPU repeats to execute one instruction: fetch the instruction, decode it, fetch operands, execute, store the result, and then check for interrupts. The state diagram shows these steps as states with arrows for the transitions.

  iac --> if --> iod --> oac --> of --> do --> oac --> os
   ^                       ^      |            ^       |
   |                       +------+            +-------+
   |                   more operands      more results
   |                                                    |
   +-- no interrupt <-- interrupt check <---------------+
                              |
                         interrupt --> interrupt processing

States of the diagram

1. Instruction address calculation (iac): find the address of the next instruction (usually PC + length).
2. Instruction fetch (if): read the instruction from memory into IR.
3. Instruction operation decoding (iod): find the operation type and the operands needed.
4. Operand address calculation (oac): if an operand is in memory (indirect or indexed), calculate its address.
5. Operand fetch (of): read the operand from memory or I/O. This pair (oac, of) repeats if there are several operands.
6. Data operation (do): the ALU performs the operation.
7. Operand store (os): write the result to memory, register or I/O. Multiple results repeat this step.

Interrupt handling

After each instruction the CPU checks for an interrupt signal. If none is pending, it goes to the next instruction. If one is pending and interrupts are enabled, the CPU:

• saves the current PC and processor status (usually on the stack),
• loads the PC with the address of the interrupt service routine,
• runs the routine, then restores the saved state and resumes the interrupted program.

The interrupt check is placed at the end of the cycle so that an instruction is never cut in half. The fetch and execute parts can also be shown as two main phases: the fetch cycle (iac, if) and the execute cycle (iod to os), with the interrupt cycle added when needed.