Four-segment instruction pipeline and space-time diagram

A pipeline divides a process into sub-operations (segments), and each segment works on a different task at the same time, like an assembly line. In the four-segment instruction pipeline, the instruction cycle is split into four stages, each with its own hardware and with registers between the stages, all working on the same clock.

The four segments

1. FI (Fetch Instruction): read the instruction from memory.
2. DA (Decode and calculate Address): decode the instruction and compute the effective address.
3. FO (Fetch Operand): read the operand from memory.
4. EX (Execute): perform the operation and store the result.

 +----+  +----+  +----+  +----+
 | FI |->| DA |->| FO |->| EX |  (registers between segments)
 +----+  +----+  +----+  +----+

Space-time diagram for 6 tasks (instructions) T1–T6

Each column is one clock cycle (one segment time tp).

Segment |  1  2  3  4  5  6  7  8  9
------------------------------------
FI      | T1 T2 T3 T4 T5 T6  .  .  .
DA      |  . T1 T2 T3 T4 T5 T6  .  .
FO      |  .  . T1 T2 T3 T4 T5 T6  .
EX      |  .  .  . T1 T2 T3 T4 T5 T6

• Once the pipe is full (clock 4), one task finishes in every clock.
• Number of clock cycles = k + n - 1 = 4 + 6 - 1 = 9, where k = 4 segments and n = 6 tasks.
• Without a pipeline, time = n × k = 6 × 4 = 24 cycles.
• Speedup = 24 / 9 = 2.67. For a large n, the speedup approaches k = 4.

Example (instruction flow)

For the program ADD R1,R2; SUB R3,R4; MUL R5,R6 ..., each instruction enters FI in a successive clock, so while T1 is in FO, T2 is in DA and T3 is in FI. Delays occur when a branch or a data dependency appears (the pipeline is flushed or stalled).