- 2073 Shrawan · 3 marks
RISC and efficient instruction pipeline
Short answer
RISC has fixed-length instructions, load/store architecture, uniform one-cycle execution, many registers, few addressing modes, delayed branches, and hardwired control, making pipeline stages balanced and efficient with CPI near 1.
"RISC has the ability to use efficient instruction pipeline". Justify the statement.
RISC makes the instruction pipeline efficient for these reasons:
- Fixed length, simple instructions are decoded quickly and in a regular way, so each takes about the same time per stage.
- Load/store architecture: only LOAD and STORE access memory, so most instructions do not need operand memory access, and few structural hazards occur.
- Uniform one-cycle execution gives balanced stage times, so the pipeline moves smoothly with CPI close to 1.
- Many registers keep operands inside the CPU, reducing memory delays.
- Few addressing modes make address calculation simple.
- Delayed branch lets the compiler fill the slot after a branch, hiding the branch penalty.
- Hardwired control is fast and has no microcode delays.
✓ Answer checked by Claude Opus 5.5 (high effort)
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