Pipeline hazards and solutions

A hazard is a condition that prevents the next instruction in the pipeline from executing in its clock cycle, so the pipeline must stall and performance falls.

Types of hazards and their solution

1. Structural (resource) hazard: two instructions need the same hardware resource at the same time, for example both an instruction fetch and an operand fetch need the memory.

• Solutions: separate instruction and data memories (caches), duplicate or pipeline the resource, add more ports, or stall one instruction.

2. Data hazard: an instruction depends on the result of an earlier instruction that is not yet finished. Types: RAW (read after write, true dependency), WAR and WAW (name dependencies). Example: ADD R1, R2, R3 followed by SUB R4, R1, R5; SUB needs R1 before ADD writes it.

• Solutions: operand forwarding (bypassing) passes the ALU output directly to the next input; hardware interlock (stall) detects the dependency and delays the instruction; compiler (software) scheduling rearranges instructions or inserts NOPs; delayed load; register renaming for WAR/WAW.

3. Control (branch) hazard: a branch changes the PC, so instructions already fetched after it may be wrong and must be discarded.

• Solutions: prefetch the target (fetch both paths), branch target buffer, branch prediction (static or dynamic), delayed branch (compiler fills the slot after the branch with a useful instruction), loop buffer, and flushing the pipeline when the guess is wrong.

 Time:        1   2   3   4   5   6
 ADD R1,..    FI  DA  FO  EX
 SUB .,R1     .   FI  DA  --  FO  EX   <- stalled until R1 is ready