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Pipelining and multi-stage pipeline

Short answer

Pipelining overlaps instruction execution by splitting it into stages like IF (fetch), ID (decode), EX (execute), MEM (memory), WB (write back). This increases throughput, ideally one instruction per cycle, though latency remains unchanged. Hazards are managed with forwarding and stalls.

What do you mean by pipelining? Explain (with a diagram) the stages of a pipeline, e.g. 5-stage or 6-stage pipelining.

Pipelining is a technique that overlaps the execution of several instructions by splitting instruction processing into stages, each handled by separate hardware. Like an assembly line, a new instruction enters the pipeline every clock cycle, so throughput increases (ideally one instruction per cycle) even though the latency of a single instruction does not fall.

Stages of a 5-stage pipeline

  1. IF - Instruction Fetch: read the instruction from memory at PC; PC <- PC + 1.
  2. ID - Instruction Decode: decode the opcode and read the register operands.
  3. EX - Execute: the ALU performs the operation or computes the address.
  4. MEM - Memory access: read or write data memory (load/store).
  5. WB - Write Back: write the result to the register file.

(The standard 6-stage pipeline uses: FI fetch instruction, DI decode instruction, CO calculate operand (effective) address, FO fetch operands, EI execute instruction, WO write operand/result.)

Timing diagram

 Cycle:   1   2   3   4   5   6   7   8
 Inst 1:  IF  ID  EX  MEM WB
 Inst 2:      IF  ID  EX  MEM WB
 Inst 3:          IF  ID  EX  MEM WB
 Inst 4:              IF  ID  EX  MEM WB

Without pipelining, 4 instructions need 20 cycles; with the pipeline they need 8 (k + n − 1 = 5 + 4 − 1).

Hazards (structural, data, control/branch) can stall the pipeline; they are handled by forwarding, stalls and branch prediction.

✓ Answer checked by Claude Opus 5.5 (high effort)

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