Six stage pipeline technique

Pipelining overlaps the execution of several instructions by dividing instruction processing into stages. Each stage works on a different instruction in each clock cycle, like stations of an assembly line.

The six stages

1. FI – Fetch Instruction: read the instruction from memory.
2. DI – Decode Instruction: find the opcode and operand specifiers.
3. CO – Calculate Operands: compute the effective address of each operand.
4. FO – Fetch Operands: read the operands from memory or registers.
5. EI – Execute Instruction: perform the operation.
6. WO – Write Operand: store the result.

Example: 4 instructions, one clock per stage

Time    1  2  3  4  5  6  7  8  9
I1     FI DI CO FO EI WO         
I2        FI DI CO FO EI WO      
I3           FI DI CO FO EI WO   
I4              FI DI CO FO EI WO

• Without pipelining, 4 instructions take 4 × 6 = 24 clock cycles.
• With the six-stage pipeline: k + (n − 1) = 6 + 3 = 9 cycles.
• After the pipeline is full (cycle 6), one instruction completes in each cycle.
• For n = 9 instructions: 54 cycles without pipeline; 6 + 8 = 14 cycles with it, speed-up = 54/14 ≈ 3.86.

Speed-up = n·k / (k + n − 1), which approaches k = 6 for a large number of instructions.

Pipeline hazards (resource conflicts, data dependence, branches) can stall the pipeline and reduce the speed-up.