Chapter 6 · Watch, then practise
Advanced Topics
Study how processors share work and resources, then compare instruction-set styles and signal-processing hardware. The chapter links parallelism to the operating-system support needed to coordinate it.
6 questions · 6 with related videos. Matches are based on playlist titles; broader background matches are labeled.
What to study
- Shared-bus, multiport-memory and central-control multiprocessors
- Real parallel execution and time-sliced concurrency
- Flynn classification: SISD, SIMD, MISD and MIMD
- Instruction, thread and process parallelism
- Communication, synchronization, resource allocation and deadlock
- Accumulator and register-based architectures; RISC and CISC
- Digital signal processors
Chapter playlists
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Notes
Introduction to RTOS Part 12 - Multicore Systems | Digi-Key Electronics
DigiKey · 16:27
Choose a video · 2 lectures
Supplementary multicore and task-scheduling lessons for comparing parallel execution with scheduled tasks.
1. Concurrency versus parallel execution
Why does switching between two processes on one core not prove that both execute simultaneously?
Time slicing interleaves progress. Simultaneous execution needs multiple execution resources. Two processes can therefore be concurrent without running in parallel. A multicore machine can run different processes at the same time, subject to scheduling and available resources.
flynn's classification or taxonomy in parallel computing in hindi
Last moment tuitions · 4:20
The chapter playlist’s Flynn-taxonomy lesson matches the SIMD-versus-MIMD classification topic.
2. Classify two parallel workloads
Classify one instruction applied across many array elements and separate programs executing on separate processors.
The first is SIMD: one instruction stream acts on multiple data items. Independent instruction streams acting on independent data are MIMD. Classification concerns instruction and data streams, not simply the number of processor packages.
Amdahl's Law in COA: Basics, Proof, and CPU Performance Explained
Engineering Funda · 9:28
Supplementary Amdahl-law lesson; the 20% serial fraction and four-processor calculation are worked below.
3. An ideal speedup limit
Assume 20% of a program is serial and 80% divides perfectly over four processors. Ignore overhead. What speedup follows?
Normalized time is 0.20 + 0.80/4 = 0.40, so speedup is 1/0.40 = 2.5×. This is an ideal model; communication and synchronization increase real execution time. Even unlimited processors cannot remove the serial 20%.
L-2.13: RISC vs CISC | Computer Organization & Architecture
Gate Smashers · 8:22 · Background lecture
Existing COA RISC-versus-CISC lesson provides architectural background; the RV32I-specific load/store sequence is below.
4. Load-store architecture in practice
In RV32I, can an integer ADD directly add two memory locations? Describe the required sequence.
No. RV32I arithmetic operates on registers. Load the operands into registers, add them, then store the result if memory must change. This explains a load-store ISA; it does not establish that every instruction takes one cycle or that every RISC implementation has the same performance.
Software Defined Radio with HackRF by Michael Ossmann, Lesson 10: Filters
Great Scott Gadgets · 43:22
Supplementary FIR-filter lesson; the publisher’s lesson outline explicitly includes multiply-accumulate operations.
5. Why multiply-accumulate matters
A four-tap filter computes y[n] = h[0]x[n] + h[1]x[n−1] + h[2]x[n−2] + h[3]x[n−3]. What hardware operation is repeated?
Each term multiplies a sample by a coefficient and adds it to an accumulator: four multiply-accumulate steps per output sample. DSP hardware and memory access paths are designed to sustain such repeated work. Required throughput depends on both tap count and sample rate.
Daisy Chain, Polling & Independent Request bus contention methods | Bus Contention & Bus Arbitration
Engineering Funda · 13:35
Choose a video · 2 lectures
Combines bus-contention methods with multiprocessor background; the scaling argument is explained below.
6. Shared memory is not free communication
Why can adding processors to a common-bus multiprocessor fail to give proportional speedup?
Processors compete for the same bus and memory service. More compute units do not create more shared-bus bandwidth. Coordination and contention can limit throughput even when enough independent work exists.