Chapter 2 · Watch, then practise
Central Processing Unit
Trace operands, results and the next instruction address through a simple CPU.
3 questions · 3 with related videos. Matches are based on playlist titles; broader background matches are labeled.
What to study
- Instruction cycle
- Registers and ALU
- Effective addresses
- Conditional branches
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Notes
L-2.4: Register Mode | Addressing Mode | Computer Organisation and Architecture
Gate Smashers · 4:39
Choose a video · 2 lectures
Pairs register operands with instruction-cycle background; the particular ADD trace is explained below.
1. Instruction execution
Trace a register-to-register ADD instruction in a simple CPU.
Fetch the instruction using the program counter. Decode its opcode and register fields. Read the two source registers, select addition in the ALU, then write the result into the destination register. Select the next sequential instruction address. A single-cycle implementation performs this work within one clock period; other implementations split it across cycles.
L-2.10: Base Register Addressing Mode || Computer Organisation and Architecture
Gate Smashers · 6:58
Covers base-register addressing; use the question’s base and displacement values in the calculation below.
2. Address versus value
A load uses base R1 = 2000 and displacement 24. What is loaded?
The effective address is 2000 + 24 = 2024, assuming byte addressing and a byte displacement. The destination receives the value stored at that address, not the number 2024. Address calculation and memory reading are separate operations. Instruction width and alignment rules must come from the particular ISA.
L-1.12: Program Control Instructions(Types of Control Instructions) | Computer Organization
Gate Smashers · 10:51
Supplementary program-control lesson for conditional branches and the instruction sequence.
3. Branch control
Why does a conditional branch need more than an ALU result?
It needs a condition result and a target address. Control uses the condition to select either the target or the sequential address as the next program counter. The CPU must also suppress unintended state changes, such as a memory write, while executing the branch.