IVT in 8086 and ISR execution sequence

Use of the interrupt vector table

The IVT occupies 00000H–003FFH and holds 256 four-byte vectors (IP then CS). For interrupt type n, the 8086 reads the new IP from address 4n and the new CS from 4n + 2. The type number comes from the INT n instruction, from a fixed value (types 0–4), or from the interrupt controller during the INTA' cycles of INTR. Because the table is in memory, the user can change a vector and so install his or her own ISR.

Complete sequence (example: INT 21H)

Assume SP = 1000H and the next instruction address is CS:IP.

1. The 8086 fetches and decodes INT 21H (CDH 21H). IP now points to the next instruction.
2. Push flags: SP ← SP − 2 = 0FFEH; flag register stored.
3. Clear IF and TF (IF = 0, TF = 0) to disable INTR and single stepping.
4. Push CS: SP ← 0FFCH.
5. Push IP (return address): SP ← 0FFAH.
6. Calculate the vector address: 21H × 4 = 0084H.
7. IP ← word at 00084H, CS ← word at 00086H.
8. The next instruction is fetched from the new CS:IP, i.e. the ISR starts.
9. The ISR executes (it saves registers with PUSH if it uses them).
10. IRET (CFH): pop IP (SP = 0FFCH), pop CS (SP = 0FFEH), pop flags (SP = 1000H). Original IF and TF are restored.
11. The main program continues with the instruction after INT 21H.

 Stack after step 5 (grows down)
 SP -> 0FFAH : IP (return)
       0FFCH : CS (return)
       0FFEH : FLAGS
       1000H : (old top)

For hardware INTR the sequence is the same, except that step 1 is replaced by two INTA' cycles that bring the type number.