- 2071 Magh · 2+6 marks
ISR, IVT and type 0 to 4 interrupts
Short answer
An ISR is the routine executed on interrupt. The IVT is a 1 KB table at 00000H storing 256 vectors (4 bytes each) for type n at address 4n. Types 0–4 are: 0 divide error, 1 single step, 2 NMI, 3 breakpoint, 4 overflow.
Define Interrupt Service Routine (ISR) and Interrupt Vector Table (IVT). Explain type 0 to type 4 interrupt of 8086.
Interrupt Service Routine (ISR)
An ISR (interrupt handler) is the routine that the processor executes in response to an interrupt. It performs the task needed by the interrupting source, and ends with IRET to return to the interrupted program.
Interrupt Vector Table (IVT)
The IVT is a 1 KB table at memory addresses 00000H–003FFH that holds 256 vectors. Each vector has 4 bytes (IP low, IP high, CS low, CS high), giving the address of the ISR for that interrupt type. The vector of type n is at 4 × n.
Type 0 to type 4 interrupts
| Type | Name | Vector at | Occurs when |
|---|---|---|---|
| 0 | Divide error | 00000H | Result of DIV/IDIV is too large for the destination, or divisor is 0 |
| 1 | Single step | 00004H | Trap flag TF = 1; interrupt after each instruction, used by debuggers |
| 2 | Non-maskable interrupt | 00008H | Rising edge on NMI pin; power failure, parity error |
| 3 | Breakpoint | 0000CH | One-byte instruction INT 3 (opcode CCH); debuggers insert it to stop a program at a point |
| 4 | Overflow | 00010H | INTO instruction executed with overflow flag OF = 1 |
- Types 0, 1 and 2 are invoked automatically (by an error, the trap flag or the NMI pin); types 3 and 4 are caused by instructions.
- None of types 0–4 needs the INTA' cycle or an external type number, and none of them is masked by IF.
- Types 5–31 are reserved by Intel and types 32–255 are available to users.
✓ Answer checked by Claude Opus 5.5 (high effort)
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