- 2073 Magh · 8 marks
EI, DI, SIM, RIM and ISR address
Short answer
EI enables maskable interrupts after next instruction; DI disables them. SIM sets masks, resets RST7.5 flip-flop, outputs serial data. RIM reads mask/pending/IE and SID. Fixed vectors: TRAP=0024H, RST7.5=003CH, RST6.5=0034H, RST5.5=002CH. INTR obtains address from external device via INTA'.
Explain the purpose of the EI, DI, SIM and RIM instructions of the 8085 processor while using interrupts. Describe how the 8085 obtains the starting address of the interrupt service routine for each of the hardware interrupts.
Purpose of the instructions
| Instruction | Opcode | Purpose |
|---|---|---|
| EI | FBH | Enable interrupts: sets the interrupt enable flip-flop, so INTR, RST 5.5, 6.5, 7.5 can be accepted. The effect starts after the next instruction, so a RET can complete first. |
| DI | F3H | Disable interrupts: resets the flip-flop; INTR and RST 5.5/6.5/7.5 are ignored. TRAP is not affected. |
| SIM | 30H | Set Interrupt Mask: uses the accumulator to set or clear the masks of RST 5.5/6.5/7.5, to reset the RST 7.5 flip-flop, and to output serial data on SOD. |
| RIM | 20H | Read Interrupt Mask: puts the mask bits, pending interrupt bits, the IE flag and the serial input SID into the accumulator. |
SIM accumulator format
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| SOD | SDE | X | R7.5 | MSE | M7.5 | M6.5 | M5.5 |
- MSE = 1 allows the mask bits M7.5–M5.5 to be changed; M = 1 masks that interrupt.
- R7.5 = 1 resets the RST 7.5 flip-flop. SDE = 1 enables serial output of bit SOD.
Example: to enable RST 6.5 only, MVI A,0DH ; SIM ; EI (MSE = 1, M7.5 = 1, M6.5 = 0, M5.5 = 1).
RIM format: SID, I7.5, I6.5, I5.5, IE, M7.5, M6.5, M5.5 (D7 to D0).
How the starting address of the ISR is obtained
When an interrupt is accepted, the 8085 pushes the PC on the stack and loads the PC with a fixed address, as follows.
| Interrupt | Vector (starting address) |
|---|---|
| TRAP | 0024H |
| RST 7.5 | 003CH |
| RST 6.5 | 0034H |
| RST 5.5 | 002CH |
| INTR | Not fixed |
- These addresses are 8 × n for the restart number n: TRAP acts as RST 4.5, so 4.5 × 8 = 36 = 24H; 5.5 × 8 = 44 = 2CH; 6.5 × 8 = 52 = 34H; 7.5 × 8 = 60 = 3CH.
- For these four inputs the vector is internal, so no INTA' is needed. Normally a JMP to the real ISR is stored at the vector address, because only a few bytes are available between vectors.
- For INTR, the 8085 sends INTA' and the external device puts an instruction on the data bus. It is usually RST n (vector 8 × n, from 0000H to 0038H) or a CALL instruction with a 16-bit address, so the device decides the ISR address.
✓ Answer checked by Claude Opus 5.5 (high effort)
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