Interrupt processing in 8086

A hardware interrupt in the 8086 comes from an external device on the INTR pin (maskable, level-triggered) or the NMI pin (non-maskable, rising-edge triggered, type 2). The 8086 services it after finishing the current instruction.

INTR interrupt (maskable) – sequence

1. An external device (usually through an 8259A PIC) raises INTR.
2. At the end of the current instruction the 8086 checks INTR. It is accepted only if the interrupt flag IF = 1.
3. The 8086 runs two INTA' (interrupt acknowledge) bus cycles. The first cycle tells the PIC that the request has been accepted. In the second cycle the PIC places the 8-bit interrupt type number (0–255) on D7–D0, and the 8086 reads it.
4. The 8086 pushes the flag register on the stack (SP ← SP − 2).
5. It clears IF and TF, so that no other INTR or single-stepping takes place inside the routine.
6. It pushes CS, then IP (the return address of the next instruction).
7. It multiplies the type number by 4 to get the vector address. It loads the new IP from addresses 4×type and 4×type + 1, and the new CS from 4×type + 2 and 4×type + 3 of the interrupt vector table.
8. The interrupt service routine (ISR) executes. If nesting is wanted, the ISR executes STI.
9. IRET at the end pops IP, CS and the flags, and the main program resumes.

NMI interrupt

• NMI is not affected by IF and needs no INTA' cycles and no external type number.
• The type is fixed as 2, so the vector is read from addresses 00008H–0000BH.
• The remaining steps (push flags, clear IF and TF, push CS and IP, load CS:IP, run the ISR, IRET) are the same.
• It is used for power failure and memory parity errors.

 Device -> INTR ----------------> 8086
 8086 -> INTA' (1st): "acknowledged"
 8086 -> INTA' (2nd): PIC puts type n on D7-D0
 Push FLAGS, CS, IP;  IF=0, TF=0
 IP <- [4n], CS <- [4n+2]  -> run ISR -> IRET

Example: type 40H → vector at 4×40H = 0100H; the new IP is read from 00100H–00101H and CS from 00102H–00103H.