Sequence of steps when interrupt occurs

When a device requests an interrupt, the processor follows this sequence.

1. The device sends an interrupt request signal (for example INTR).
2. The processor finishes the instruction that is being executed. It does not stop in the middle of an instruction.
3. The processor checks whether the interrupt is allowed (the interrupt-enable flag is set and no higher-priority interrupt is in service).
4. It sends an interrupt acknowledge signal (INTA') to the device.
5. It saves the current status: the contents of the program counter (return address) and, in the 8086, the flags, are pushed onto the stack. Further interrupts are disabled.
6. It finds the address of the interrupt service routine (ISR). This is either fixed (RST, TRAP in 8085) or taken from the interrupt vector table using the type number (8086).
7. The PC (CS:IP) is loaded with that address, and the ISR executes. The ISR saves any registers it uses and services the device.
8. The ISR ends with a return instruction (RET in 8085, IRET in 8086). The saved values are popped from the stack; on the 8085 the ISR executes EI before RET to enable interrupts again, while IRET on the 8086 restores IF with the flags.
9. The processor continues the interrupted program from the next instruction.