IC manufacturing steps; top-down F = xz + y

Steps to manufacture an IC

1. Wafer preparation: purify silicon, grow a single crystal (Czochralski), slice, polish, clean.
2. Oxidation: grow a SiO2 layer on the wafer.
3. Photolithography: coat photoresist, align the mask, expose and develop.
4. Etching: remove the oxide or film in the exposed windows.
5. Doping: diffusion or ion implantation to make wells and source/drain regions.
6. Gate formation: thin gate oxide and polysilicon gates, patterned by lithography.
7. Deposition and metallisation: insulating layers, contacts and metal interconnect layers.
8. Repeat steps 2-7 for every mask layer.
9. Wafer test, dicing, packaging and final test.

Top-down view of F = xz + y

F is made as F = NOT(G), where G = NOT(xz + y).

VDD ---+-------------+
       |             |
    PMOS(x)       PMOS(z)      x, z in parallel
       |             |
       +------+------+
              |
           PMOS(y)             in series with y
              |
              +-----------------> G --[INV]--> F
              |
       +------+------+
       |             |
    NMOS(y)       NMOS(x)      y in parallel with
       |             |         (x in series with z)
      GND         NMOS(z)
                     |
                    GND

Pull-down: y in parallel with (x series z). Pull-up: y in series with (x parallel z). Total 8 transistors with the output inverter.

Top-down (stick) layout:

 VDD ================================ metal
       |    |    |
     +-+----+----+-+  p+ diffusion
     |  x    z    y |  vertical poly
     +-+----+----+-+  lines cross
       +---- G ----   metal output
     +-+----+----+-+  both rows
     |  x    z    y |  n+ diffusion
     +-+----+----+-+
       |    |    |
 GND ================================ metal

Each poly-diffusion crossing forms a transistor; metal and contacts connect the drains to G, the sources to VDD/GND, and G to the output inverter (not shown).