Skip to main content

Semi-custom ASIC and manufacturing steps

Short answer

Semi-custom ASIC uses gate arrays (pre-made transistors, custom metal) or standard cells (custom all layers). The two-input NAND with two PMOS parallel and two NMOS series is fabricated by n-well formation, active isolation, gate oxide/poly patterning, n+/p+ source/drain implants, contact etching and metal interconnect for VDD, output and GND.

Briefly explain semi-custom (ASIC) IC technology and write about its types. Explain IC manufacturing steps of the circuit given below. [Figure: CMOS circuit with supply VDD: two PMOS transistors (width 2) in parallel from VDD to output F, driven by A and B; two NMOS transistors (width 2) in series from F to ground, driven by A and B]

Semi-custom (ASIC) technology

In semi-custom IC technology the chip is built from pre-designed logic cells or pre-fabricated transistors; the designer only chooses cells and designs their placement and interconnection. This lowers design time and cost compared with full custom, at some loss of performance and density.

Types

  • Gate array: wafers with an array of unconnected transistors are made in advance; only the metal interconnect masks are custom. Fast and cheap, but less dense.
  • Standard cell: a library of pre-designed cells (gates, flip-flops) is placed in rows and routed; all mask layers are custom. Denser and faster than gate arrays, but costlier.
  • (Programmable logic devices such as FPGAs are sometimes counted as a third, user-programmed type.)

Manufacturing steps for the given circuit

The circuit is a 2-input CMOS NAND gate: F = (A·B)'. Two PMOS in parallel (VDD to F, gates A and B) and two NMOS in series (F to ground, gates A and B), all of width 2.

  1. Start with a p-type wafer; form an n-well (photolithography and implantation of phosphorus) for the PMOS transistors.
  2. Field oxide / isolation (LOCOS or STI) separates the transistors; the active areas are defined with a mask. The width of the active area under each gate sets the transistor width (2 units).
  3. Gate oxide and polysilicon: grow a thin gate oxide, deposit poly-Si, and pattern the two gate lines (A and B) by lithography and etching. The width of each poly line sets the channel length.
  4. Source/drain implants: an n+ implant (arsenic) in the p-substrate for the two series NMOS, with the poly self-aligning the gates; a p+ implant (boron) in the n-well for the two PMOS. Each implant uses its own lithography mask.
  5. Insulator and contacts: deposit oxide, and open contact holes by lithography and etching.
  6. Metal 1: deposit and pattern aluminium to connect the PMOS sources to VDD, the two PMOS drains and the top NMOS drain together as output F, and the bottom NMOS source to ground.
  7. Passivation, wafer test, dicing and packaging.
 Cross-section of the two kinds of transistor (simplified)
   PMOS in n-well                 NMOS in p-substrate
  [p+] gate [p+]                  [n+] gate [n+]
  ---------------------           -------------------
       n-well                       p-type substrate

✓ Answer checked by Claude Opus 5.5 (high effort)

Related questions

All Embedded System chapter 8 questions →