Full-custom, semi-custom and PLD design steps

Three schemes are used to implement an IC design. They differ in how much of the chip is designed by the user.

Full-custom

1. Specification and architecture.
2. Logic/circuit design: transistor-level schematics, sizing for speed and power.
3. Physical layout drawn by hand: every transistor and wire as polygons.
4. Design rule check, extraction and simulation (repeat until correct).
5. Generate a full set of masks.
6. Fabricate wafers, test, package.

Semi-custom (gate array / standard cell)

1. Specification; write the design in VHDL/Verilog or schematic.
2. Simulate and synthesise to a netlist of library cells.
3. Place the cells and route the wires (automatically by tools).
4. Verify timing and design rules.
5. Make masks: only metal/contact layers (gate array) or all layers (standard cell).
6. Fabricate, test, package.

PLD (programmable logic device: PAL, CPLD, FPGA)

1. Specification; write the design in VHDL/Verilog or schematic.
2. Simulate and synthesise.
3. Map to the device's logic blocks, place and route using the vendor tool.
4. Generate the programming (bit) file.
5. Program the standard device (fuses, EPROM or SRAM cells), then test. No masks or fabrication by the user; it can be re-programmed.

Comparison