- 2070 Bhadra · 8 marks
Execution of LDA 8B7FH with timing
Short answer
LDA 8B7FH (opcode 3AH) loads A from address 8B7FH. It uses four cycles: opcode fetch, two reads to form address (7FH, 8BH), and a data read, totaling 13 T-states.
Explain the execution of instruction LDA 8B7FH with the help of timing diagram.
LDA 8B7FH (opcode 3AH) copies the byte stored at memory location 8B7FH into the accumulator. It is a 3-byte instruction (3AH, 7FH, 8BH) with 4 machine cycles and 13 T-states. Assume it is stored at 2000H.
Execution step by step
- M1, opcode fetch (T1-T4): PC = 2000H appears on the address bus (20H on A15-A8, 00H on AD7-AD0); ALE = 1 in T1 so that the low byte is latched. IO/M = 0, S1 = S0 = 1. RD goes low in T2; the memory returns 3AH, read by the CPU into the instruction register at T3. T4 decodes the opcode. PC = 2001H.
- M2, memory read (T1-T3): address 2001H; RD low in T2-T3; byte 7FH (low order address) is stored in register Z. PC = 2002H.
- M3, memory read (T1-T3): address 2002H; byte 8BH (high order address) is stored in W. PC = 2003H.
- M4, memory read (T1-T3): address WZ = 8B7FH; 8BH on A15-A8 and 7FH on AD7-AD0 with ALE high in T1. RD is low during T2-T3 and the data byte from 8B7FH is read into A.
| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| M1 (opcode fetch, 4T) | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 | |
| T3 | 20H | 3AH (opcode in) | 0 | RD low, rises at end | 0 1 1 | |
| T4 | - | - | 0 | none (decode) | 0 1 1 | |
| M2 (memory read, 3T) | T1 | 20H | 01H | 1 | - | 0 1 0 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 20H | 7FH (data in) | 0 | RD low, rises at end | 0 1 0 | |
| M3 (memory read, 3T) | T1 | 20H | 02H | 1 | - | 0 1 0 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 20H | 8BH (data in) | 0 | RD low, rises at end | 0 1 0 | |
| M4 (memory read, 3T) | T1 | 8BH | 7FH | 1 | - | 0 1 0 |
| T2 | 8BH | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 8BH | data (data in) | 0 | RD low, rises at end | 0 1 0 |
Status: M1 = (IO/M,S1,S0) 0 1 1 ; M2,M3,M4 = 0 1 0
Total T-states = 4 + 3 + 3 + 3 = 13
✓ Answer checked by Claude Opus 5.5 (high effort)
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