SISO shift register with timing diagram

A serial-in serial-out (SISO) shift register accepts data one bit at a time on a single input line and delivers it one bit at a time from the last flip-flop. A 4-bit SISO register is four D flip-flops in cascade with a common clock.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

The Q output of each flip-flop drives the D input of the next, so at every clock edge each bit moves one place to the right: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation (example: storing 1011)

Assume the register is cleared (all 0) and the data 1011 is entered LSB first, so the serial input sequence is 1, 1, 0, 1 on clocks 1 to 4. After clock 4 the word is fully stored; clocks 5 to 8 (with input 0) shift it out at QD.

• Storing (clocks 1-4): after 4 clocks QA QB QC QD = 1011, i.e. the number 1011 with QA as MSB.
• Retrieving: the LSB appears at QD after clock 4, and clocks 5, 6 and 7 bring out the remaining bits. An n-bit word takes n clocks to load; since the first bit is then already at the output, n - 1 more clocks read out the rest (n more clocks empty the register).

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾‾‾‾‾|___|‾‾‾|________________
QA    _|‾‾‾‾‾‾‾|___|‾‾‾|______________
QB    _____|‾‾‾‾‾‾‾|___|‾‾‾|__________
QC    _________|‾‾‾‾‾‾‾|___|‾‾‾|______
QD    _____________|‾‾‾‾‾‾‾|___|‾‾‾|__

Each waveform is the one above it delayed by one clock period. SISO registers are used as digital delay lines (delay = n clock periods) and for serial data transmission.