SISO and SIPO shift register circuits

Both registers are chains of D flip-flops with a common clock in which Q of one stage drives D of the next. They differ only in how the output is taken.

Serial In Serial Out (SISO)

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

Output only from the last flip-flop (QD).

Serial In Parallel Out (SIPO)

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Outputs from every flip-flop (QA to QD) are available together.

Explanation of SIPO shift register

1. Clear all flip-flops (QA..QD = 0000).
2. Apply the data bits one at a time at Din, LSB first. At each rising clock edge every bit moves one stage to the right: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.
3. After 4 clocks the full word is stored and is read in parallel from QA QB QC QD.

Example, storing 1011 (serial input 1, 1, 0, 1):

       1   2   3   4
CLK   _|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾‾‾‾‾|___|‾‾‾|
QA    _|‾‾‾‾‾‾‾|___|‾‾
QB    _____|‾‾‾‾‾‾‾|__
QC    _________|‾‾‾‾‾‾
QD    _____________|‾‾

After the 4th clock the outputs show QA QB QC QD = 1011. Thus SIPO converts serial data to parallel form (used in serial receivers), while SISO only delays the data by 4 clock periods.