Registers

A serial-in serial-out (SISO) shift register accepts data one bit at a time on a single input line and delivers it one bit at a time from the last flip-flop. A 4-bit SISO register is four D flip-flops in cascade with a common clock.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |     |   |     |   |     |   |     |
   +->|>    |+->|>    |+->|>    |+->|>    |
   |  +-----+|  +-----+|  +-----+|  +-----+
 CLK---------+---------+---------+

The Q output of each flip-flop drives the D input of the next, so at every clock edge each bit moves one place to the right: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation (example: storing 1011)

Assume the register is cleared (all 0) and the data 1011 is entered LSB first, so the serial input sequence is 1, 1, 0, 1 on clocks 1 to 4. After clock 4 the word is fully stored; clocks 5 to 8 (with input 0) shift it out at QD.

• Storing (clocks 1-4): after 4 clocks QA QB QC QD = 1011, i.e. the number 1011 with QA as MSB.
• Retrieving: the LSB appears at QD after clock 4; then clocks 5, 6, 7 bring out the remaining bits. A complete word of n bits takes n clocks to load and n further clocks (n-1 after the first bit is visible) to read out.

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾‾‾‾‾|___|‾‾‾|________________
QA    _|‾‾‾‾‾‾‾|___|‾‾‾|______________
QB    _____|‾‾‾‾‾‾‾|___|‾‾‾|__________
QC    _________|‾‾‾‾‾‾‾|___|‾‾‾|______
QD    _____________|‾‾‾‾‾‾‾|___|‾‾‾|__

Each waveform is the one above it delayed by one clock period. SISO registers are used as digital delay lines (delay = n clock periods) and for serial data transmission.

A parallel-in serial-out (PISO) shift register loads all bits of a word at the same time (parallel) and then sends them out one bit per clock on a single line (serial). A 4-bit PISO register uses four D flip-flops, a SHIFT/LOAD' control and a 2-to-1 selector (two AND gates and an OR gate) in front of each flip-flop.

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1011

Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 1, 0, 1, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _____|‾‾‾|__________
QC      _|‾‾‾|___|‾‾‾|______
QD      _|‾‾‾‾‾‾‾|___|‾‾‾|__

The whole 4-bit word is stored in one clock and retrieved in four clock periods; PISO registers are used for parallel-to-serial conversion, e.g. in serial communication (UART transmitter).

A serial-in serial-out (SISO) shift register takes data one bit at a time at a single input and gives it out one bit at a time at a single output. A 4-bit SISO register is a chain of four D flip-flops (A, B, C, D) driven by a common clock.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

Data enters FF-A only and leaves from FF-D only. At each rising edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1011

The register is cleared to 0000 first. The data is entered LSB first: serial input = 1, 1, 0, 1 at clocks 1 to 4, then 0s.

• Storing (clocks 1 to 4): after clock 4, QA QB QC QD = 1011, i.e. 1011 is held with QA as MSB.
• Retrieving (serial out at QD): the output after clocks 4, 5, 6, 7 is 1, 1, 0, 1, which is 1011 read LSB first. After clock 8 the register is empty again.
• A 4-bit SISO register needs 4 clocks to load and 4 clocks to empty (3 more clocks after the first bit appears).

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾‾‾‾‾|___|‾‾‾|________________
QA    _|‾‾‾‾‾‾‾|___|‾‾‾|______________
QB    _____|‾‾‾‾‾‾‾|___|‾‾‾|__________
QC    _________|‾‾‾‾‾‾‾|___|‾‾‾|______
QD    _____________|‾‾‾‾‾‾‾|___|‾‾‾|__

Each Q waveform is the previous one delayed by one clock period.

Uses: time delay of n clock periods (digital delay line) and serial data transfer.

A serial-in parallel-out (SIPO) shift register takes data serially, one bit per clock, and makes all stored bits available at the same time on separate output lines. A 4-bit SIPO register is four cascaded D flip-flops with a common clock and an output taken from every flip-flop. The example below uses the data 1010.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1010

The register is first cleared (0000). The data is applied LSB first, so the serial input is 0, 1, 0, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1010, which is 1010 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|________________
QA    _____|‾‾‾|___|‾‾‾|______________
QB    _________|‾‾‾|___|‾‾‾|__________
QC    _____________|‾‾‾|___|‾‾‾|______
QD    _________________|‾‾‾|___|‾‾‾|__

SIPO registers are used for serial-to-parallel conversion, e.g. in a UART receiver.

A serial-in parallel-out (SIPO) shift register receives data bit by bit on one input line and presents the complete word on separate parallel output lines. A 4-bit SIPO register is made of four D flip-flops in cascade with a common clock; Q of every stage is an output.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1101

The register is first cleared (0000). The data is applied LSB first, so the serial input is 1, 0, 1, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1101, which is 1101 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾|___|‾‾‾‾‾‾‾|________________
QA    _|‾‾‾|___|‾‾‾‾‾‾‾|______________
QB    _____|‾‾‾|___|‾‾‾‾‾‾‾|__________
QC    _________|‾‾‾|___|‾‾‾‾‾‾‾|______
QD    _____________|‾‾‾|___|‾‾‾‾‾‾‾|__

SIPO registers convert serial data into parallel form (serial-to-parallel converter), as in a serial receiver.

A PISO (parallel-in serial-out) shift register accepts all bits of a word at once and shifts them out one bit per clock. It is built from four D flip-flops; a control line SHIFT/LOAD' selects, through AND-OR gates, whether each flip-flop takes its parallel input bit (load) or the output of the flip-flop on its left (shift).

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1101

Parallel inputs: PA PB PC PD = 1 1 0 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1101. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 0, 1, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 0, 1, 1, i.e. 1101 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _|‾‾‾‾‾‾‾|__________
QC      _____|‾‾‾‾‾‾‾|______
QD      _|‾‾‾|___|‾‾‾‾‾‾‾|__

A 4-bit parallel-in serial-out (PISO) shift register stores a 4-bit word applied on four parallel lines in one clock and then shifts it out bit by bit on a single serial output. It uses four D flip-flops, a common clock and a SHIFT/LOAD' control that, through a 2-to-1 AND-OR selector at each D input, chooses between parallel data and the output of the previous stage. The working is illustrated with the word 1011.

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1011

Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 1, 0, 1, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _____|‾‾‾|__________
QC      _|‾‾‾|___|‾‾‾|______
QD      _|‾‾‾‾‾‾‾|___|‾‾‾|__

Working principle in short: load in parallel, then shift right. A 4-bit word needs 1 load clock plus 3 shift clocks to transmit all bits. PISO registers are used for parallel-to-serial conversion in data transmission.

The register asked here (named SIPO) is a 4-bit serial-in parallel-out shift register. It accepts data one bit per clock at a single serial input and gives the whole word on four parallel outputs QA to QD. Its last output QD also works as a serial output, so the same circuit acts as a SISO register when the bits are taken out from QD by further clocks.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1010

The register is first cleared (0000). The data is applied LSB first, so the serial input is 0, 1, 0, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1010, which is 1010 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|________________
QA    _____|‾‾‾|___|‾‾‾|______________
QB    _________|‾‾‾|___|‾‾‾|__________
QC    _____________|‾‾‾|___|‾‾‾|______
QD    _________________|‾‾‾|___|‾‾‾|__

Note the serial output at QD after clocks 4, 5, 6, 7: 0, 1, 0, 1 (1010 read LSB first), which is the serial-out mode of the same register.

A PISO register takes a word in parallel (all bits together) and gives it out serially (one bit per clock). The 4-bit version uses four D flip-flops with a SHIFT/LOAD' control and an AND-OR selector at each D input.

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1010

Parallel inputs: PA PB PC PD = 1 0 1 0 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1010. The LSB (0) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn.
3. Serial output after clocks 1 to 4: 0, 1, 0, 1, i.e. 1010 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _____|‾‾‾|__________
QC      _|‾‾‾|___|‾‾‾|______
QD      _____|‾‾‾|___|‾‾‾|__

Both registers are chains of D flip-flops with a common clock in which Q of one stage drives D of the next. They differ only in how the output is taken.

Serial In Serial Out (SISO)

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

Output only from the last flip-flop (QD).

Serial In Parallel Out (SIPO)

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Outputs from every flip-flop (QA to QD) are available together.

Explanation of SIPO shift register

1. Clear all flip-flops (QA..QD = 0000).
2. Apply the data bits one at a time at Din, LSB first. At each rising clock edge every bit moves one stage to the right: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.
3. After 4 clocks the full word is stored and is read in parallel from QA QB QC QD.

Example, storing 1011 (serial input 1, 1, 0, 1):

       1   2   3   4
CLK   _|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾‾‾‾‾|___|‾‾‾|
QA    _|‾‾‾‾‾‾‾|___|‾‾
QB    _____|‾‾‾‾‾‾‾|__
QC    _________|‾‾‾‾‾‾
QD    _____________|‾‾

After the 4th clock the outputs show QA QB QC QD = 1011. Thus SIPO converts serial data to parallel form (used in serial receivers), while SISO only delays the data by 4 clock periods.

A parallel-in serial-out (PISO) shift register stores a word applied to its parallel inputs in one clock and then shifts it out one bit per clock. A 4-bit PISO register uses four D flip-flops; a SHIFT/LOAD' line selects (through AND-OR gates) either the parallel input or the previous stage's output for each flip-flop.

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1001

Parallel inputs: PA PB PC PD = 1 0 0 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1001. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 0, 0, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 0, 0, 1, i.e. 1001 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _____|‾‾‾|__________
QC      _________|‾‾‾|______
QD      _|‾‾‾|_______|‾‾‾|__

A register is a group of flip-flops (usually D type) with a common clock that stores a binary word; an n-bit register has n flip-flops. A shift register can also move the stored bits left or right at each clock. Registers are classified by how data is entered and taken out.

1. Serial In Serial Out (SISO)

Data enters one bit per clock at FF-A and leaves one bit per clock from FF-D.

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

A 4-bit SISO takes 4 clocks to load and 4 to empty; used as a delay line.

2. Serial In Parallel Out (SIPO)

Data enters serially; after n clocks all bits are read at once from QA to QD.

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Used for serial-to-parallel conversion (e.g. serial receiver).

3. Parallel In Serial Out (PISO)

All bits are loaded together when SH/LD' = 0; with SH/LD' = 1 they are shifted out one per clock at QD.

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

Used for parallel-to-serial conversion (e.g. serial transmitter).

4. Parallel In Parallel Out (PIPO)

Each flip-flop has its own input and output; at one clock edge the whole word is stored and is immediately available. There is no shifting.

     PA        PB        PC        PD
     |         |         |         |
  +-----+   +-----+   +-----+   +-----+
  |D    |   |D    |   |D    |   |D    |
  |>   Q|   |>   Q|   |>   Q|   |>   Q|
  +-----+   +-----+   +-----+   +-----+
   ^  |      ^  |      ^  |      ^  |
 CLK  QA       QB        QC        QD
 (common clock; no connection between stages)

Used as a storage (buffer) register, e.g. accumulator or latch for data.

5. Bidirectional and universal shift registers

• Bidirectional: a control line (RIGHT/LEFT') selects shifting right ($D_B = Q_A$) or left ($D_B = Q_C$) through AND-OR gates.
• Universal (e.g. IC 74194): can hold, shift right, shift left and parallel load, selected by mode inputs S1 S0 (00 hold, 01 shift right, 10 shift left, 11 load).

Shift register

A shift register is a group of flip-flops connected in a chain, with a common clock, that stores a binary word and moves (shifts) it one bit position to the right or left at each clock pulse. An n-bit shift register has n flip-flops. Depending on how data is entered and taken out, there are SISO, SIPO, PISO, PIPO and bidirectional/universal shift registers. They are used for data storage, serial-parallel conversion, time delay, and ring/Johnson counters.

4-bit PISO shift register

The PISO register loads 4 bits in parallel in one clock and sends them out serially, one bit per clock. The example data is 1011.

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1011

Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 1, 0, 1, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _____|‾‾‾|__________
QC      _|‾‾‾|___|‾‾‾|______
QD      _|‾‾‾‾‾‾‾|___|‾‾‾|__

A serial-in parallel-out (SIPO) shift register takes data serially, one bit per clock pulse, into the first flip-flop and shifts it along the chain; the outputs of all flip-flops are available together, so after n clocks an n-bit word can be read in parallel.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Four D flip-flops share a common clock. $D_A = D_{in}$, $D_B = Q_A$, $D_C = Q_B$, $D_D = Q_C$, so at every rising edge each stored bit moves one stage right, and QA..QD are taken out as parallel outputs.

Function:

1. Clear the register (0000).
2. Apply the bits at Din, one per clock, LSB first.
3. After 4 clocks the word sits in QA QB QC QD and is read at once.
4. Further clocks (with Din = 0) push the data out through QD and the register clears.

Shift mechanism for 1010 (up to 9 clocks)

Serial input = 0, 1, 0, 1 at clocks 1 to 4 (1010 LSB first), and 0 afterwards.

• Clock 4: QA QB QC QD = 1010: the word 1010 is stored and read in parallel.
• Clocks 5 to 8: the data moves out through QD. QD after clocks 4, 5, 6, 7 is 0, 1, 0, 1 (1010 read LSB first), and the register is clear after clock 8.
• Clock 9: all outputs remain 0000 since only 0s are entering.

Timing diagram

       1   2   3   4   5   6   7   8   9
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|____________________
QA    _____|‾‾‾|___|‾‾‾|__________________
QB    _________|‾‾‾|___|‾‾‾|______________
QC    _____________|‾‾‾|___|‾‾‾|__________
QD    _________________|‾‾‾|___|‾‾‾|______

A bidirectional shift register can shift its data either to the right or to the left, selected by a mode control line RIGHT/LEFT' (M). It uses four D flip-flops with a common clock and a 2-to-1 AND-OR selector in front of each D input.

Circuit

 One stage (stage B) of the register:
 QA ------------->+-----+
 R/L' ---+------->| AND |--+
         |        +-----+  |  +----+
         |                 +->| OR |--> DB
         |        +-----+  +->|    |
         +-[NOT]->| AND |--+  +----+
 QC ------------->+-----+
 DB = M.QA + M'.QC        (M = R/L')

 Full register:
 DR ->[sel]->FF-A <-> [sel]->FF-B <-> [sel]->FF-C
       <-> [sel]->FF-D <-[sel]<- DL
 DA = M.DR + M'.QB     DB = M.QA + M'.QC
 DC = M.QB + M'.QD     DD = M.QC + M'.DL

• M = 1 (shift right): the upper AND gates are enabled. Each flip-flop takes the output of the stage on its left: $QA \leftarrow DR,\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. Serial data enters at DR and leaves at QD.
• M = 0 (shift left): the lower AND gates are enabled. Each flip-flop takes the output of the stage on its right: $QD \leftarrow DL,\ QC \leftarrow QD,\ QB \leftarrow QC,\ QA \leftarrow QB$. Serial data enters at DL and leaves at QA.

Truth (function) table

Example and timing diagram

Starting from 0000: shift right for 4 clocks with DR = 1, 0, 1, 1; then shift left for 3 clocks with DL = 0, 1, 1.

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
R/L'  ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|____________
DR    ‾‾‾|___|‾‾‾‾‾‾‾|____________
DL    ___________________|‾‾‾‾‾‾‾|
QA    _|‾‾‾|___|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾
QB    _____|‾‾‾|___|‾‾‾|___|‾‾‾|__
QC    _________|‾‾‾|___|‾‾‾|___|‾‾
QD    _____________|‾‾‾|___|‾‾‾‾‾‾

During clocks 1 to 4 the bits move towards QD; from clock 5 the direction reverses and the bits move towards QA while new bits enter at QD. Bidirectional (universal) shift registers such as IC 74194 are used for multiplication/division by 2 and in serial data handling.

A 4-bit serial-in serial-out (SISO) shift register is four D flip-flops connected in a chain with a common clock. Data enters one bit per clock at the first flip-flop and comes out one bit per clock from the last flip-flop.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

Data enters FF-A only and leaves from FF-D only. At each rising edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1101

The register is cleared to 0000 first. The data is entered LSB first: serial input = 1, 0, 1, 1 at clocks 1 to 4, then 0s.

• Storing (clocks 1 to 4): after clock 4, QA QB QC QD = 1101, i.e. 1101 is held with QA as MSB.
• Retrieving (serial out at QD): the output after clocks 4, 5, 6, 7 is 1, 0, 1, 1, which is 1101 read LSB first. After clock 8 the register is empty again.
• A 4-bit SISO register needs 4 clocks to load and 4 clocks to empty (3 more clocks after the first bit appears).

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾|___|‾‾‾‾‾‾‾|________________
QA    _|‾‾‾|___|‾‾‾‾‾‾‾|______________
QB    _____|‾‾‾|___|‾‾‾‾‾‾‾|__________
QC    _________|‾‾‾|___|‾‾‾‾‾‾‾|______
QD    _____________|‾‾‾|___|‾‾‾‾‾‾‾|__

Each Q waveform is the previous one delayed by one clock period.

Uses: delaying a serial signal by 4 clock periods and serial data transfer.

In a serial-in parallel-out (SIPO) shift register, bits are fed one by one into the first flip-flop and shifted along at every clock; once all bits are in, they are read at the same time from the outputs of all flip-flops. For the 4-bit sequence 1001 we need four D flip-flops with a common clock.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1001

The register is first cleared (0000). The data is applied LSB first, so the serial input is 1, 0, 0, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1001, which is 1001 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾|_______|‾‾‾|________________
QA    _|‾‾‾|_______|‾‾‾|______________
QB    _____|‾‾‾|_______|‾‾‾|__________
QC    _________|‾‾‾|_______|‾‾‾|______
QD    _____________|‾‾‾|_______|‾‾‾|__

So storing 1001 takes 4 clock pulses (input 1, 0, 0, 1, since 1001 is the same read either way), and retrieving is done in one step by reading QA QB QC QD = 1001 in parallel.

Applications of shift registers

• Temporary data storage (buffer registers).
• Serial-to-parallel and parallel-to-serial conversion (UART, serial communication).
• Time delay of serial data by n clock periods.
• Arithmetic: shift left/right to multiply or divide by 2.
• Ring counters and Johnson (twisted ring) counters, sequence generators.

3-bit switched tail ring counter (Johnson counter)

A switched tail (twisted ring) counter, also called a Johnson counter, is a shift register whose complemented output of the last flip-flop is fed back to the input of the first. An n-flip-flop Johnson counter has 2n states, so 3 flip-flops give a mod-6 counter.

   +--------------------------------+
   |                          QC'   |
   |  +-----+   +-----+   +------+  |
   +->|D  QA|-->|D  QB|-->|D   QC|  |
      |>    |   |>    |   |>  QC'|--+
      +-----+   +-----+   +------+
         ^         ^         ^
 CLK ----+---------+---------+
 All FFs cleared to 000 at the start.

Working

1. All flip-flops are cleared: QA QB QC = 000. Then $D_A = \overline{Q_C} = 1$.
2. At each clock the data shifts right ($QB \leftarrow QA,\ QC \leftarrow QB$) and $QA \leftarrow \overline{Q_C}$.
3. 1s fill the register from the left (100, 110, 111); once QC = 1, 0s enter (011, 001, 000), and the cycle repeats after 6 clocks.

Each state is decoded by one 2-input AND gate (last column), which is simpler than decoding a binary counter.

Timing diagram

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
QA    _|‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾
QB    _____|‾‾‾‾‾‾‾‾‾‾‾|__________
QC    _________|‾‾‾‾‾‾‾‾‾‾‾|______

Each output is a square wave of frequency $f_{CLK}/6$, shifted by one clock from the previous one. If the counter enters an unused state (010 or 101) it cycles in a wrong loop, so extra correction logic or a proper reset is needed.

Shift register and its applications

A shift register is a chain of flip-flops with a common clock that stores binary data and shifts it one position left or right at each clock pulse.

Applications:

• Temporary data storage (buffer registers).
• Serial-to-parallel and parallel-to-serial conversion (UART, serial communication).
• Time delay of serial data by n clock periods.
• Arithmetic: shift left/right to multiply or divide by 2.
• Ring counters and Johnson (twisted ring) counters, sequence generators.

4-bit ring counter

A ring counter is a shift register whose last output is connected back to the first input, so a single 1 circulates around the ring. A 4-bit ring counter has 4 states (mod-4, mod-n in general).

   +-----------------------------------------+
   |   PRE         CLR       CLR       CLR   |
   |  +-----+   +-----+   +-----+   +-----+  |
   +->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--+
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
 CLK ---^---------^---------^---------^
 Start pulse: PRESET A, CLEAR B, C, D -> 1000

Working principle

1. A start pulse presets FF-A and clears FF-B, C, D, so QA QB QC QD = 1000.
2. At each rising clock edge every bit moves one place right and QD goes back to QA ($D_A = Q_D$).
3. The single 1 travels A to B to C to D and back to A, giving the sequence 1000, 0100, 0010, 0001, 1000, ...
4. Exactly one output is high at a time, so no decoder is needed; each output is high for one clock period out of every four.

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
QA    ‾|___________|‾‾‾|___________|‾‾
QB    _|‾‾‾|___________|‾‾‾|__________
QC    _____|‾‾‾|___________|‾‾‾|______
QD    _________|‾‾‾|___________|‾‾‾|__

The frequency at each output is $f_{CLK}/4$. Ring counters are used as sequence (timing) generators and for controlling steps in sequential operations. The drawback is that n flip-flops give only n states.

A ring counter is a shift register (usually of D flip-flops) whose output of the last stage is fed back to the input of the first stage. It is initialised with a single 1 (e.g. 1000) and this 1 circulates through the flip-flops, one stage per clock.

   +-----------------------------------------+
   |   PRE         CLR       CLR       CLR   |
   |  +-----+   +-----+   +-----+   +-----+  |
   +->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--+
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
 CLK ---^---------^---------^---------^
 Start pulse: PRESET A, CLEAR B, C, D -> 1000

Operation (4-bit): after a preset/clear, QA QB QC QD = 1000. At each clock the bits shift right with $D_A = Q_D$, giving 1000, 0100, 0010, 0001 and back to 1000.

Features

• n flip-flops give n states (mod-n counter), e.g. 4 flip-flops give mod-4.
• Only one output is 1 at any time, so it is self-decoding: no decoder gates are needed.
• Each output frequency is $f_{CLK}/n$.
• It must be preset to a valid starting pattern; a wrong start (e.g. 0000 or 1100) circulates forever.
• Uses: timing/sequence generation, stepper motor control, control-step signals in CPUs.

A variation with $\overline{Q_D}$ fed back (switched tail or Johnson counter) gives 2n states.