Counters

A mod-5 synchronous counter counts 0, 1, 2, 3, 4 and returns to 0 (5 states). Since $2^2 < 5 \le 2^3$, 3 flip-flops (Q2 Q1 Q0, Q2 = MSB) are needed. All flip-flops get the same clock (positive edge triggered J-K), and the J, K inputs are found from the excitation table.

Step 1: state diagram

 000 -> 001 -> 010 -> 011 -> 100
  ^                            |
  +----------------------------+
 Unused: 101, 110, 111 (don't cares)

Step 2: J-K excitation table

Step 3: state table with flip-flop inputs

States 5, 6 and 7 never occur, so all their inputs are don't cares (x).

Step 4: K-maps and simplified expressions

K-map for J2
Q2\Q1Q0  00  01  11  10
  0       0   0   1   0
  1       x   x   x   x

K-map for K2
Q2\Q1Q0  00  01  11  10
  0       x   x   x   x
  1       1   x   x   x

K-map for J1
Q2\Q1Q0  00  01  11  10
  0       0   1   x   x
  1       0   x   x   x

K-map for K1
Q2\Q1Q0  00  01  11  10
  0       x   x   1   0
  1       x   x   x   x

K-map for J0
Q2\Q1Q0  00  01  11  10
  0       1   x   x   1
  1       0   x   x   x

K-map for K0
Q2\Q1Q0  00  01  11  10
  0       x   1   1   x
  1       x   x   x   x

$$\begin{aligned} J_2 &= Q_1 Q_0, & K_2 &= 1 \\ J_1 &= Q_0, & K_1 &= Q_0 \\ J_0 &= \overline{Q_2}, & K_0 &= 1 \end{aligned}$$

Step 5: logic diagram

     +--------+    +--------+    +--------+
 J0->|J0   Q0 |J1->|J1   Q1 |J2->|J2   Q2 |
 K0->|K0  Q0' |K1->|K1  Q1' |K2->|K2  Q2' |
     |>  FF0  |    |>  FF1  |    |>  FF2  |
     +--------+    +--------+    +--------+
 CLK ---^-------------^-------------^
 Input connections:
   J0 <- Q2'            K0 <- 1 (HIGH)
   J1 <- Q0             K1 <- Q0
   J2 <- AND(Q1, Q0)    K2 <- 1 (HIGH)

Timing diagram

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0    _|‾‾‾|___|‾‾‾|_______|‾‾‾|__
Q1    _____|‾‾‾‾‾‾‾|___________|‾‾
Q2    _____________|‾‾‾|__________

The counter goes 000, 001, 010, 011, 100, 000, ...; Q2 is high for one clock in five, so the output frequency is $f_{CLK}/5$.

Unused states check: with these equations, 101 goes to 010, 110 goes to 010 and 111 goes to 000, so the counter returns to the main sequence by itself (self-starting).

A mod-12 asynchronous (ripple) up counter counts 0 to 11 (0000 to 1011) and then resets to 0000. Since $2^3 < 12 \le 2^4$, 4 T flip-flops are needed. Each flip-flop has T = 1, so it toggles at every active clock edge it receives.

Clock connections for positive edge triggering

In an up counter, a flip-flop must toggle when the previous output goes 1 to 0. With positive (rising) edge triggered flip-flops, this 1-to-0 change of Q is the same instant as the 0-to-1 change of $\overline{Q}$. So:

• FF0 is clocked by the external CLK.
• FF1 is clocked by $\overline{Q_0}$, FF2 by $\overline{Q_1}$, FF3 by $\overline{Q_2}$.

Reset logic

The count must stop at 11, so the first unwanted state 12 = 1100 is detected. In 1100 only Q3 and Q2 are 1 (and no earlier count 0 to 11 has both Q3 and Q2 = 1), so

$$\overline{CLR} = \overline{Q_3 Q_2}$$

A 2-input NAND gate drives the active-low CLEAR inputs of all flip-flops. As soon as 1100 appears, the NAND output goes 0 and all flip-flops clear to 0000 (state 1100 exists only for a few ns).

Circuit

      T=1          T=1          T=1          T=1
    +------+     +------+     +------+     +------+
CLK>|> FF0 | +-->|> FF1 | +-->|> FF2 | +-->|> FF3 |
    |   Q0'|-+   |   Q1'|-+   |   Q2'|-+   |      |
    | CLR' |     | CLR' |     | CLR' |     | CLR' |
    +------+     +------+     +------+     +------+
 Outputs: Q0 (LSB), Q1, Q2, Q3 (MSB)
 Q3 --+
      +-->[NAND]--> CLR' of all four flip-flops
 Q2 --+

Count sequence

At the 12th clock the counter reaches 1100 for a moment and is immediately cleared to 0000.

Timing diagram

      1   2   3   4   5   6   7   8   9   10  11  12
CLK  _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0   _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|__
Q1   _____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|__
Q2   _____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__________________
Q3   _____________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__

Q0 toggles at every rising edge of CLK; Q1 toggles when Q0 falls; Q2 when Q1 falls; Q3 when Q2 falls. Q3 is high for counts 8 to 11, so Q3 has frequency $f_{CLK}/12$. (In a real ripple counter each change is delayed by one flip-flop delay from the previous stage.)

A mod-6 synchronous counter goes through 6 states, 0 to 5 (000 to 101), and then returns to 000. Since $2^2 < 6 \le 2^3$, 3 T flip-flops (Q2 Q1 Q0, Q2 = MSB) with a common clock are used. A T flip-flop must have T = 1 whenever its output has to change.

Step 1: state diagram

 000 -> 001 -> 010 -> 011 -> 100 -> 101
  ^                                   |
  +-----------------------------------+
 Unused: 110, 111 (don't cares)

Step 2: T excitation table

Step 3: state table with flip-flop inputs

Step 4: K-maps

K-map for T2
Q2\Q1Q0  00  01  11  10
  0       0   0   1   0
  1       0   1   x   x

K-map for T1
Q2\Q1Q0  00  01  11  10
  0       0   1   1   0
  1       0   0   x   x

K-map for T0
Q2\Q1Q0  00  01  11  10
  0       1   1   1   1
  1       1   1   x   x

• $T_0$: all used states are 1, so $T_0 = 1$.
• $T_1$: 1s at states 1 and 3; state 5 is 0, so $T_1 = Q_0 \overline{Q_2}$.
• $T_2$: 1s at states 3 and 5; with don't care 7: $T_2 = Q_1 Q_0 + Q_2 Q_0$.

$$\begin{aligned} T_0 &= 1 \\ T_1 &= Q_0\,\overline{Q_2} \\ T_2 &= Q_0 Q_1 + Q_0 Q_2 = Q_0 (Q_1 + Q_2) \end{aligned}$$

Step 5: logic diagram

  1           T1            T2
  |           |             |
 +----+      +----+        +----+
 |T0  |      |T1  |        |T2  |
 | FF0|--Q0  | FF1|--Q1    | FF2|--Q2
 |>   |      |>   |        |>   |
 +----+      +----+        +----+
  ^           ^             ^
 CLK ---------+-------------+   (common clock)

 T1 = Q0 AND Q2'       : one 2-input AND
 T2 = Q0.Q1 + Q0.Q2    : two ANDs + one OR
                         (= Q0 AND (Q1 OR Q2))

Timing diagram

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0    _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾
Q1    _____|‾‾‾‾‾‾‾|______________
Q2    _____________|‾‾‾‾‾‾‾|______

The output sequence is 000, 001, 010, 011, 100, 101, 000, ...; Q2 is high for two clocks out of six, so its frequency is $f_{CLK}/6$.

Unused states: 110 goes to 111 and 111 goes to 010, so the counter enters the main count by itself (self-starting).

A synchronous decade (BCD / mod-10) counter counts from 0000 to 1001 (0 to 9) and returns to 0000 on the 10th clock pulse. All flip-flops receive the same clock, so they change state together.

Step 1: Number of flip-flops and states

• 10 states are needed, so $2^n \ge 10 \Rightarrow n = 4$ T flip-flops ($Q_3Q_2Q_1Q_0$, $Q_0$ = LSB).
• Used states: 0000 to 1001. Unused states 1010 to 1111 are taken as don't cares (X).
• T flip-flop excitation: $T = Q \oplus Q^+$ (T = 1 whenever the flip-flop must change).

Step 2: Excitation table

Step 3: K-maps (X = don't care)

$T_0 = 1$ for every state. The other inputs:

Step 4: Simplified equations

$$\begin{aligned} &T_3 = Q_3Q_0 + Q_2Q_1Q_0 \\ &T_2 = Q_1Q_0 \\ &T_1 = \overline{Q_3}Q_0 \\ &T_0 = 1 \end{aligned}$$

So two 2-input AND gates ($\overline{Q_3}Q_0$ and $Q_1Q_0$), one 3-input AND ($Q_2Q_1Q_0$), one 2-input AND ($Q_3Q_0$) and one OR gate for $T_3$ are needed.

Step 5: Circuit diagram

   +-----+       +-----+       +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1 T2>|T   Q|-Q2 T3>|T   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
   |     |       |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
T0 = 1          T1 = Q3'.Q0
T2 = Q1.Q0      T3 = Q3.Q0 + Q2.Q1.Q0

Step 6: Timing diagram (negative-edge clock)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1

$Q_0$ toggles on every clock edge, $Q_1$ toggles when $Q_0 = 1$ (except at count 9), $Q_2$ toggles when $Q_1Q_0 = 1$, and $Q_3$ goes high at count 8 and returns low after count 9. The counter therefore divides the clock frequency by 10 ($f_{Q_3} = f_{clk}/10$).

Self-starting check: the unused states go back into the count (1010→1011→0110, 1100→1101→0100, 1110→1111→0010), so the counter cannot lock out.

An asynchronous up/down counter is a ripple counter that can count either upward (0, 1, 2, …, 7) or downward (7, 6, …, 0) depending on a mode control input M. Only the first flip-flop gets the external clock; each later flip-flop is clocked by the previous stage.

Principle

For negative-edge triggered JK flip-flops with $J = K = 1$ (toggle mode):

• Up count: the next flip-flop must toggle when the previous output goes $1 \to 0$, so it is clocked from $Q$.
• Down count: the next flip-flop must toggle when the previous output goes $0 \to 1$, i.e. when $\overline{Q}$ goes $1 \to 0$, so it is clocked from $\overline{Q}$.

A 2-input AND-OR (or MUX) between stages selects $Q$ or $\overline{Q}$:

$$CLK_1 = M\,Q_0 + \overline{M}\,\overline{Q_0}, \qquad CLK_2 = M\,Q_1 + \overline{M}\,\overline{Q_1}$$

M = 1 gives up counting, M = 0 gives down counting.

Circuit

 M=1: UP    M=0: DOWN      (all J = K = 1)

       +-----+  Q0 --[AND]--+
CLK --o| FF0 |       M      +--[OR]--> CLK of FF1
       +-----+ Q0' --[AND]--+
                     M'
       +-----+  Q1 --[AND]--+
 ... -o| FF1 |       M      +--[OR]--> CLK of FF2
       +-----+ Q1' --[AND]--+
                     M'

Outputs $Q_2Q_1Q_0$ (Q0 = LSB) give the count.

Operation

1. M = 1 (up): FF0 toggles on every falling clock edge. When $Q_0$ falls from 1 to 0, FF1 toggles; when $Q_1$ falls, FF2 toggles. Sequence: 000, 001, 010, …, 111, 000.
2. M = 0 (down): FF1 toggles when $Q_0$ rises (its $\overline{Q_0}$ falls), and FF2 toggles when $Q_1$ rises. Sequence: 000, 111, 110, …, 001, 000.

Timing diagram: up mode (M = 1)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   0

Timing diagram: down mode (M = 0)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    7   6   5   4   3   2   1   0

Points to note

• Each stage waits for the previous one, so the total delay is $3\,t_{pd}$ and short false states appear during transitions.
• The mode M should be changed only when the clock is steady; switching M can create an extra edge at the next stage and give a wrong count.

A 3-bit Gray code counter steps through the 3-bit Gray sequence, in which only one bit changes between successive counts: 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. A synchronous design with JK flip-flops is given below.

Step 1: Flip-flops

8 states, so 3 JK flip-flops ($Q_2Q_1Q_0$) with a common clock. No unused states.

JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

Step 2: Excitation table

Step 3: K-maps

Step 4: Equations

$$\begin{aligned} &J_2 = Q_1\overline{Q_0},\quad K_2 = \overline{Q_1}\overline{Q_0} \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_2Q_0 \\ &J_0 = Q_2Q_1 + \overline{Q_2}\overline{Q_1},\quad K_0 = Q_2\overline{Q_1} + \overline{Q_2}Q_1 \end{aligned}$$

So $J_0 = \overline{Q_2 \oplus Q_1}$ (XNOR) and $K_0 = Q_2 \oplus Q_1$ (XOR).

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = XNOR(Q2,Q1)   K0 = XOR(Q2,Q1)
J1 = Q2'.Q0        K1 = Q2.Q0
J2 = Q1.Q0'        K2 = Q1'.Q0'

Gates needed: one XOR, one XNOR (or XOR + NOT) and four 2-input AND gates.

Step 6: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Cnt  000  001 011 010 110 111 101 100 000

Only one output changes at each clock edge, which is the main advantage of a Gray code counter (no decoding glitches, low noise).

An asynchronous (ripple) decade counter is a mod-10 ripple counter: it counts 0000 to 1001 and resets to 0000 on the 10th clock pulse.

Design

• Number of flip-flops: $2^n \ge 10 \Rightarrow n = 4$ JK flip-flops, negative-edge triggered, all with $J = K = 1$ (toggle mode).
• The clock drives FF0 only; $Q_0$ clocks FF1, $Q_1$ clocks FF2, $Q_2$ clocks FF3.
• The counter must reset when the count reaches 10 = 1010. In 1010, $Q_3 = 1$ and $Q_1 = 1$; this is the first count in which both are 1. So a 2-input NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR inputs of all flip-flops.

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Count sequence

Operation

On each falling clock edge FF0 toggles. Each later flip-flop toggles when the previous output falls from 1 to 0, so the count goes up by one per clock. At the 10th pulse the counter momentarily enters 1010; NAND output goes low and clears all flip-flops to 0000 within a few nanoseconds. The state 1010 lasts only for this short time, so the counter shows 0 to 9.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

(A very short spike on $Q_1$ at the 10th edge, caused by the 1010 state, is ignored in the ideal diagram.) $Q_3$ has a frequency of $f_{clk}/10$, so the circuit is also a divide-by-10 circuit. IC 7490 is a ready-made decade ripple counter.

Sequential logic circuit

A sequential logic circuit is a circuit whose output depends on the present inputs and on the past history (stored state) of the circuit. It contains memory elements (flip-flops or latches) and a feedback path; flip-flops, registers and counters are examples.

Mod-10 negative-edge ripple counter

A mod-10 (decade) ripple counter has 10 states, 0000 to 1001. Since $2^3 < 10 \le 2^4$, four JK flip-flops are used.

Connections

• All J and K inputs are tied to logic 1, so every flip-flop toggles on its active (falling) clock edge.
• The external clock goes to FF0 only. $Q_0$ is the clock of FF1, $Q_1$ of FF2 and $Q_2$ of FF3 (negative-edge triggering means a stage toggles when the previous Q falls from 1 to 0, which gives up counting).
• Count 10 = 1010 must not be held. It is the first state with $Q_3 = Q_1 = 1$, so $\overline{Q_3Q_1}$ (NAND) is fed to the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Operation

1. Initially all flip-flops are cleared: $Q_3Q_2Q_1Q_0 = 0000$.
2. Every falling clock edge toggles FF0. Whenever $Q_0$ goes 1→0, FF1 toggles; whenever $Q_1$ goes 1→0, FF2 toggles; whenever $Q_2$ goes 1→0, FF3 toggles. The count rises 0, 1, 2, …, 9.
3. On the 10th falling edge the outputs try to become 1010. At once the NAND output goes low and clears all flip-flops, so the counter returns to 0000. The false state 1010 exists only for a few nanoseconds.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

Each output changes on the falling edge of the signal that clocks it. $Q_3$ is high only for counts 8 and 9, and its frequency is $f_{clk}/10$. In a real circuit each stage adds a propagation delay $t_{pd}$, so the outputs ripple and a narrow spike appears on $Q_1$ at the reset.

Synchronous vs asynchronous counter

Design of 3-bit synchronous down counter (JK)

A 3-bit down counter counts 7, 6, 5, …, 0 and then returns to 7. Three JK flip-flops ($Q_2Q_1Q_0$) share one clock.

Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

K-maps

$J_0$ and $K_0$ are 1 in every row (Q0 toggles every clock), so $J_0 = K_0 = 1$. $J_1$ and $K_1$ have the same map, and so do $J_2$ and $K_2$.

Equations

$$\begin{aligned} &J_2 = \overline{Q_1}\overline{Q_0},\quad K_2 = \overline{Q_1}\overline{Q_0} \\ &J_1 = \overline{Q_0},\quad K_1 = \overline{Q_0} \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

In words, a stage toggles when all lower bits are 0 (the "borrow" condition), just as an up counter stage toggles when all lower bits are 1.

Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = K1 = Q0'
J2 = K2 = Q1'.Q0'   (one 2-input AND gate)

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    7   6   5   4   3   2   1   0

All outputs change together on the falling clock edge, so no ripple delay or false state appears.

Ripple counter

A ripple counter is an asynchronous counter in which only the first flip-flop is driven by the external clock and each following flip-flop is clocked by the output of the previous one. The change of state "ripples" through the chain, one flip-flop after another.

Design: asynchronous mod-11 up counter

1. Number of flip-flops: a mod-11 counter needs 11 states (0 to 10). $2^3 = 8 < 11 \le 2^4 = 16$, so 4 flip-flops are needed. JK flip-flops with $J = K = 1$ (toggle) and negative-edge clocks are used.
2. Clocking: CLK → FF0; $Q_0$ → clock of FF1; $Q_1$ → FF2; $Q_2$ → FF3. With falling-edge triggering, using Q as the next clock gives an up count.
3. Reset logic: the counter should go from 10 (1010) back to 0. So it must be cleared as soon as it reaches 11 = 1011. In 1011, $Q_3 = Q_1 = Q_0 = 1$. In the states 0 to 10, these three bits are never all 1, so a 3-input NAND gate of $Q_3, Q_1, Q_0$ drives the active-low CLEAR of all flip-flops.

$$\overline{CLR} = \overline{Q_3\,Q_1\,Q_0}$$

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
Q1  ---| NAND |o--> CLR of all FFs (active low)
Q0  ---|      |

Count table

Operation: each falling clock edge toggles FF0, and each stage toggles when the previous output falls 1→0, so the count increases by one per pulse. On the 11th pulse the state 1011 appears for a moment, the NAND output becomes 0, all flip-flops clear, and the count restarts from 0000.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|_______
Cnt  0    1   2   3   4   5   6   7   8   9   10  0

$Q_3$ is high for counts 8, 9 and 10, so the output frequency at $Q_3$ is $f_{clk}/11$.

A mod-5 Gray code counter steps through the first five codes of the 3-bit Gray sequence, changing only one bit per clock:

$$000 \to 001 \to 011 \to 010 \to 110 \to 000$$

Step 1: Flip-flops and unused states

• 5 states need $n = 3$ JK flip-flops ($Q_2Q_1Q_0$), all clocked together on the negative (falling) edge.
• Unused states 100, 101 and 111 are treated as don't cares (X).

Step 2: Excitation table

JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

Step 3: K-maps

$K_2$: Q2 = 1 only in state 110, where it must reset, and the other cells are X, so $K_2 = 1$.

Step 4: Equations

$$\begin{aligned} &J_2 = Q_1\overline{Q_0},\quad K_2 = 1 \\ &J_1 = Q_0,\quad K_1 = Q_2 \\ &J_0 = \overline{Q_1},\quad K_0 = Q_1 \end{aligned}$$

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q1'    K0 = Q1
J1 = Q0     K1 = Q2
J2 = Q1.Q0' K2 = 1

Only one AND gate and one inverter are needed ($\overline{Q_1}$ and $\overline{Q_0}$ can be taken from the flip-flops' $\overline{Q}$ outputs, so in practice just one 2-input AND gate).

Step 6: Check of unused states

All unused states enter the main sequence after one clock, so the counter is self-starting.

Step 7: Timing diagram (negative edge)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾|_______|‾‾‾
Q0   ____|‾‾‾‾‾‾‾|___________|‾‾‾‾‾‾‾
Cnt  000  001 011 010 110 000 001 011

Combinational vs sequential circuits

Asynchronous mod-12 counter

A mod-12 ripple counter counts 0 to 11 and returns to 0 on the 12th clock pulse. Four negative-edge JK flip-flops ($2^4 = 16 \ge 12$) are used with $J = K = 1$. CLK drives FF0, and $Q_0$, $Q_1$, $Q_2$ clock FF1, FF2, FF3.

The counter must be cleared at 12 = 1100. It is the first count with $Q_3 = Q_2 = 1$, so a 2-input NAND of $Q_3$ and $Q_2$ drives the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q2  ---|      |

Operation: FF0 toggles on every falling clock edge; each later flip-flop toggles when the previous Q falls 1→0, so the count goes 0000, 0001, …, 1011. At the 12th pulse the counter momentarily reaches 1100, the NAND output goes low and all flip-flops clear to 0000.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   10  11  0

$Q_3$ is high for counts 8 to 11, so $f_{Q_3} = f_{clk}/12$.

Definitions

• Synchronous counter: a counter in which all flip-flops are driven by the same clock pulse, so all outputs change at the same time. Logic gates decide which flip-flops toggle.
• Asynchronous (ripple) counter: a counter in which only the first flip-flop gets the external clock; each later flip-flop is clocked by the output of the previous one, so the outputs change one after another.

Design of MOD-10 synchronous counter (JK flip-flops)

Step 1: 10 states (0000–1001) need 4 JK flip-flops ($Q_3Q_2Q_1Q_0$). States 1010–1111 are don't cares.

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Step 3: K-maps (only the non-trivial ones)

$K_1 = Q_0$ and $J_2 = K_2 = Q_1Q_0$ are read the same way.

Step 4: Equations

$$\begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_0 \\ &J_2 = Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = \overline{Q_3}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

Step 5: Circuit diagram

   +-----+       +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2 J3>|J   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
K0>|K    |    K1>|K    |    K2>|K    |    K3>|K    |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
J0 = K0 = 1        J1 = Q3'.Q0   K1 = Q0
J2 = K2 = Q1.Q0    J3 = Q2.Q1.Q0  K3 = Q0

Step 6: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1

All flip-flops change together on the falling clock edge. $Q_3$ is high for counts 8 and 9, giving $f_{Q_3} = f_{clk}/10$. Unused states 10–15 return to the main count within two clocks, so the counter is self-starting.

Asynchronous counter

An asynchronous (ripple) counter is a counter in which the external clock is applied only to the first flip-flop, and every other flip-flop is clocked by the output of the preceding flip-flop. The flip-flops therefore change state one after another, not together. It is simple but slow, and it shows short false states while the change ripples through.

Design of the synchronous counter: 000, 001, 011, 111, 110, 100, 000 …

Step 1: 6 states, so 3 JK flip-flops ($Q_2Q_1Q_0$) with a common clock. Unused states: 010 and 101 (don't cares).

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Step 3: K-maps

Step 4: Equations

The minimum groups give $J_2 = Q_1$, but then the unused states form a closed loop 010 → 101 → 010, so a counter that powers up in 010 or 101 would never enter the sequence (lock-out). Taking the 1-cell 011 alone, $J_2 = Q_1Q_0$, removes this problem at the cost of one AND gate:

$$\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = \overline{Q_1} \\ &J_1 = Q_0,\quad K_1 = \overline{Q_0} \\ &J_0 = \overline{Q_2},\quad K_0 = Q_2 \end{aligned}$$

Check of unused states (with $J_2 = Q_1Q_0$)

So the counter is self-starting.

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q2'   K0 = Q2
J1 = Q0    K1 = Q0'
J2 = Q1.Q0 K2 = Q1'

This is a 3-bit Johnson (twisted-ring) counter: each flip-flop copies the one before it, and the last output is fed back inverted.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____________|‾‾‾‾‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾‾
Cnt  000  001 011 111 110 100 000 001

Synchronous sequential circuit

A synchronous sequential circuit is a sequential circuit whose state changes only at discrete instants fixed by a common clock signal (at the clock edge). All memory elements (flip-flops) are driven by the same clock, so the outputs are predictable and free of timing races.

Asynchronous decade counter

An asynchronous decade (mod-10) counter counts 0 (0000) to 9 (1001) and resets on the 10th clock pulse.

Circuit: four negative-edge triggered JK flip-flops with $J = K = 1$. CLK drives FF0; $Q_0$, $Q_1$, $Q_2$ drive the clocks of FF1, FF2, FF3. A NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Operation

1. All flip-flops are cleared first, so the count is 0000.
2. FF0 toggles on each falling edge of CLK. FF1 toggles whenever $Q_0$ goes 1→0, FF2 whenever $Q_1$ goes 1→0, FF3 whenever $Q_2$ goes 1→0. This produces the binary up count.
3. On the 10th pulse the outputs reach 1010. This is the first state with $Q_3 = Q_1 = 1$, so the NAND output goes low and clears all flip-flops to 0000. The counter therefore has 10 stable states (0–9).

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

Each stage changes on the falling edge of the stage before it. $Q_3$ gives one pulse for every 10 clock pulses ($f_{clk}/10$). Because the stages change one after another, the real outputs are delayed by $t_{pd}$ per stage and a short glitch appears at the reset (state 1010). IC 7490 is a commercial decade ripple counter.

Parallel counter

A parallel counter is another name for a synchronous counter: the clock is applied to all flip-flops in parallel, so they all change state at the same instant. Gates at the J-K (or T/D) inputs decide which flip-flops toggle.

Design: mod-6 synchronous up counter (JK)

Step 1: States. A mod-6 counter counts 0 to 5 (000 to 101) and returns to 000. $2^3 = 8 \ge 6$, so 3 JK flip-flops ($Q_2Q_1Q_0$) are used. Unused states 110 and 111 are don't cares.

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Step 3: K-maps

$J_0 = K_0 = 1$ since $Q_0$ toggles on every clock.

Step 4: Equations

$$\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0     K1 = Q0
J2 = Q1.Q0      K2 = Q0

Two 2-input AND gates are needed.

Step 6: Unused states

So the counter is self-starting.

Step 7: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1

All outputs change together at the falling clock edge; $Q_2$ gives $f_{clk}/6$.

Combinational vs sequential logic circuits

Mod-12 asynchronous down counter (negative-edge JK)

Design idea

1. 12 states need 4 flip-flops ($2^4 = 16 \ge 12$). JK flip-flops with $J = K = 1$ toggle on each falling clock edge.
2. Down counting with negative-edge clocks: a stage must toggle when the previous output goes $0 \to 1$, i.e. when its $\overline{Q}$ goes $1 \to 0$. So FF0 gets CLK, and $\overline{Q_0}$, $\overline{Q_1}$, $\overline{Q_2}$ drive the clocks of FF1, FF2, FF3.
3. Truncating to 12 states: a natural 4-bit down counter counts 15, 14, …, 0. We keep the 12 states 1111 (15) down to 0100 (4). When the count falls from 0100 to 0011, the counter is preset at once to 1111.
4. Preset logic: 0011 is the only state reached in which $Q_3 = Q_2 = 0$ (the ripple transients of the other steps never make both 0). An OR gate gives $Q_3 + Q_2 = 0$ only then, and its output drives the active-low PRESET of all four flip-flops:

$$\overline{PR} = Q_3 + Q_2$$

(If the count 11 → 0 is chosen instead, the reset state 1111 must be decoded, but 1111 also appears as a ripple transient when the count goes from 1000 to 0111, which would cause a false load. The 15 → 4 sequence avoids this.)

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3
    +-----+     +-----+     +-----+     +-----+
 (count is read from Q3 Q2 Q1 Q0; each FF has an
  active-low PRESET input)

Q3  ---|    |
       | OR |----> PRESET of all FFs (active low)
Q2  ---|    |

Count sequence

Operation: each falling clock edge toggles FF0. When $Q_0$ rises (0→1), $\overline{Q_0}$ falls and FF1 toggles, and so on, so the count decreases by one per pulse. After the 12th pulse the counter tries to enter 0011; the OR output goes low and presets all flip-flops to 1111, starting a new cycle of 12 states.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾
Q2   ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Q1   ‾‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾
Q0   ‾‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  15   14  13  12  11  10  9   8   7   6   5   4   15

$Q_3$ completes one cycle every 12 clock pulses ($f_{clk}/12$).

A BCD (decade) synchronous counter counts 0000 to 1001 and returns to 0000 on the 10th clock. All T flip-flops share the clock. A T flip-flop toggles when $T = 1$ and holds when $T = 0$, so $T = Q \oplus Q^+$.

Truth (excitation) table

4 flip-flops are needed ($2^4 = 16 \ge 10$); states 1010–1111 are don't cares.

K-map simplification

Similarly $T_2$ is 1 for states 0011 and 0111, giving $T_2 = Q_1Q_0$, and $T_0 = 1$.

$$\begin{aligned} &T_3 = Q_3Q_0 + Q_2Q_1Q_0 \\ &T_2 = Q_1Q_0 \\ &T_1 = \overline{Q_3}Q_0 \\ &T_0 = 1 \end{aligned}$$

Circuit diagram

   +-----+       +-----+       +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1 T2>|T   Q|-Q2 T3>|T   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
   |     |       |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
T0 = 1           T1 = Q3'.Q0
T2 = Q1.Q0       T3 = Q3.Q0 + Q2.Q1.Q0

Timing waveform

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1

• $Q_0$ toggles on every falling edge ($f_{clk}/2$).
• $Q_1$ toggles when $Q_0 = 1$, except at 9 where $\overline{Q_3} = 0$ blocks it.
• $Q_2$ toggles when $Q_1Q_0 = 1$ (at 3 → 4 and 7 → 8).
• $Q_3$ sets at 7 → 8 ($Q_2Q_1Q_0 = 1$) and resets at 9 → 0 ($Q_3Q_0 = 1$); its frequency is $f_{clk}/10$.

Unused states return to the count (1010→1011→0110, 1100→1101→0100, 1110→1111→0010), so the counter is self-starting.

A 4-bit asynchronous down counter counts 15, 14, 13, …, 0 and then back to 15, decreasing by one on every clock pulse. Only the first flip-flop gets the external clock.

Principle

In a down count a flip-flop must toggle when the next lower bit changes from 0 to 1 (a "borrow"). With negative-edge triggered flip-flops, a 0→1 change of $Q$ is a 1→0 change of $\overline{Q}$. So each stage is clocked from the $\overline{Q}$ of the previous stage.

Circuit

Four negative-edge JK flip-flops, all with $J = K = 1$ (toggle mode). CLK → FF0; $\overline{Q_0}$ → FF1; $\overline{Q_1}$ → FF2; $\overline{Q_2}$ → FF3. The count is read from $Q_3Q_2Q_1Q_0$.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3
    +-----+     +-----+     +-----+     +-----+

Working

1. Start with 0000. On the first falling edge FF0 toggles: $Q_0$ goes 0→1, so $\overline{Q_0}$ falls and FF1 toggles; $Q_1$ goes 0→1, so FF2 toggles; and then FF3 toggles. The count becomes 1111 (15).
2. Next edge: $Q_0$ goes 1→0, $\overline{Q_0}$ rises, so FF1 does not change: 1110 (14).
3. Next edge: $Q_0$ 0→1 toggles FF1 ($Q_1$ 1→0), which does not clock FF2: 1101 (13).
4. The count keeps falling by one per pulse: 12, 11, …, 1, 0, and then 15 again.

and continuing 0111 (7), 0110 (6), …, 0000 (0).

Timing diagram (falling-edge clock)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    15  14  13  12  11  10  9   8   7   6   5   4

Each $Q$ changes when the $Q$ of the stage before it goes high (its $\overline{Q}$ falls). In practice each stage adds a delay $t_{pd}$, so the change from 0000 to 1111 takes $4\,t_{pd}$. The circuit also divides frequency: $Q_0 = f/2$, $Q_1 = f/4$, $Q_2 = f/8$, $Q_3 = f/16$.

Synchronous sequential circuit

A synchronous sequential circuit is a sequential circuit in which all flip-flops are driven by a common clock, so the state can change only at the active clock edge. Examples: synchronous counters, shift registers, sequence detectors.

Asynchronous mod-12 counter

It counts 0 to 11 (0000 to 1011) and returns to 0 on the 12th clock pulse.

Construction

• 4 negative-edge JK flip-flops ($2^4 = 16 \ge 12$), $J = K = 1$.
• CLK → FF0; $Q_0$ → clock of FF1; $Q_1$ → FF2; $Q_2$ → FF3.
• Count 12 = 1100 is the first state with $Q_3 = Q_2 = 1$. A NAND gate of $Q_3$ and $Q_2$ drives the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q2  ---|      |

Operation

1. FF0 toggles on every falling edge; each later stage toggles when the previous Q falls 1→0, so the count rises 0, 1, 2, …, 11.
2. On the 12th pulse the outputs go from 1011 towards 1100. As soon as $Q_3 = Q_2 = 1$, the NAND output goes low and clears all flip-flops to 0000. State 1100 lasts only a few nanoseconds.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   10  11  0

$Q_3$ is high for counts 8–11, so it is a divide-by-12 output. IC 7492 is a commercial divide-by-12 ripple counter.

Synchronous over asynchronous counter

Advantages

• All flip-flops change together, so the total delay is one flip-flop delay plus one gate delay; the counter can run at a much higher clock frequency.
• No ripple, so there are no temporary false states and no glitches when outputs are decoded.
• Any count sequence (Gray, BCD, arbitrary) can be designed directly from the state table.
• Maximum frequency does not fall as more stages are added (with parallel carry).

Disadvantages

• Needs extra combinational logic (AND gates) for each stage, so the circuit is more complex and costlier.
• The clock drives every flip-flop, so the clock line has a larger load.
• Design takes more effort (excitation table, K-maps).

Design: 3-bit synchronous Gray code counter (D flip-flops)

Sequence: 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. 8 states, so 3 D flip-flops with a common clock. For a D flip-flop, $D = Q^+$, so the next-state columns give the D inputs directly.

K-maps

Equations

$$\begin{aligned} D_2 &= Q_2Q_0 + Q_1\overline{Q_0} \\ D_1 &= \overline{Q_2}Q_0 + Q_1\overline{Q_0} \\ D_0 &= Q_2Q_1 + \overline{Q_2}\overline{Q_1} = \overline{Q_2 \oplus Q_1} \end{aligned}$$

Circuit

   +-----+       +-----+       +-----+
D0>|D   Q|-Q0 D1>|D   Q|-Q1 D2>|D   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
   |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
D2 = Q2.Q0 + Q1.Q0'
D1 = Q2'.Q0 + Q1.Q0'
D0 = XNOR(Q2, Q1)

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Cnt  000  001 011 010 110 111 101 100 000

Only one output changes per clock, as required by the Gray code.

A digital clock is a chain of counters driven by a 1 Hz signal. Each counter's BCD output goes to a BCD-to-7-segment decoder (e.g. 7447/7448) which drives a seven-segment display, so hours, minutes and seconds are shown as decimal digits.

Block diagram

 AC 50 Hz -> [Shaper] -> [÷10] -> [÷5] -> 1 Hz
                                          |
   +--------------------------------------+
   v            SECONDS (00-59)
 [÷10 units] -----> [÷6 tens] -------+ 1 pulse/min
   |                   |             |
 [7447 dec]        [7447 dec]        |
 [7-seg disp]      [7-seg disp]      |
   +---------------------------------+
   v            MINUTES (00-59)
 [÷10 units] -----> [÷6 tens] -------+ 1 pulse/h
   |                   |             |
 [7447 dec]        [7447 dec]        |
 [7-seg disp]      [7-seg disp]      |
   +---------------------------------+
   v            HOURS (01-12)
 [÷10 units] -----> [tens FF] <--- reset/load logic
   |                   |
 [7447 dec]        [decoder]
 [7-seg disp]      [7-seg disp]

Working of each block

1. Time base: the 50 Hz mains (in Nepal) is stepped down and shaped into a square wave by a Schmitt trigger. Dividing by 10 and then by 5 gives exactly 1 pulse per second. (With 60 Hz mains the divider is ÷60; a 32.768 kHz crystal with a 15-stage ÷2 chain is also common.)
2. Seconds section: a mod-10 counter (7490) counts seconds units 0–9. Each time it goes from 9 to 0, its $Q_3$ output falls and clocks the mod-6 tens counter (0–5). When the tens counter reaches 6 (0110), it is reset to 0, and this reset produces one pulse per minute.
3. Minutes section: identical to the seconds section (mod-10 then mod-6, 00–59), clocked by the 1 pulse/min signal. Its output gives 1 pulse per hour.
4. Hours section: a mod-10 units counter and a single flip-flop for the tens digit (0 or 1). Gating logic makes the hours run 01 → 12 and then 01 (a 12-hour clock): when the count reaches 13, the units counter is loaded with 1 and the tens flip-flop is cleared. For a 24-hour clock, the tens counter is mod-3 and both counters are cleared at 24.
5. Decoders and displays: each BCD counter output (4 lines) feeds a BCD-to-7-segment decoder/driver, which turns on the correct segments a–g of a common-anode (7447) or common-cathode (7448) display. The hours tens digit needs only "1" or blank, so a simple driver is enough.

Summary of counters

Synchronous MOD-5 counter

A MOD-5 counter has 5 states, 000 → 001 → 010 → 011 → 100 → 000. Three JK flip-flops ($2^3 = 8 \ge 5$) share a common clock. States 101, 110, 111 are don't cares.

Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

K-maps

The other maps give $K_0 = 1$, $J_1 = K_1 = Q_0$ and $K_2 = 1$.

Equations

$$\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = 1 \\ &J_1 = Q_0,\quad K_1 = Q_0 \\ &J_0 = \overline{Q_2},\quad K_0 = 1 \end{aligned}$$

Block (circuit) diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q2'   K0 = 1
J1 = Q0    K1 = Q0
J2 = Q1.Q0 K2 = 1

Unused states: 101 → 010, 110 → 010, 111 → 000, so the counter is self-starting.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|___________|‾‾‾
Q0   ____|‾‾‾|___|‾‾‾|_______|‾‾‾|___
Cnt  0    1   2   3   4   0   1   2

$Q_2$ is high for one clock period out of five, so it divides the clock frequency by 5.

Applications of counters

• Frequency division (divide-by-N), e.g. getting 1 Hz from 50 Hz in clocks.
• Digital clocks, watches and timers.
• Counting events or objects (production lines, people counters).
• Frequency counters and digital meters.
• Counter-type and successive-approximation ADCs.
• Program counter and address generation in computers.
• Generating control sequences and timing signals.

Applications of shift registers

• Serial-to-parallel and parallel-to-serial data conversion (UART, serial communication).
• Temporary data storage and time delay.
• Ring and Johnson counters, sequence generators.
• Multiplication and division by 2 (shift left / right).
• Pseudo-random sequence generation (LFSR) and error checking (CRC).
• Keyboard scanning and display multiplexing.

The seconds section of a digital clock counts 1 Hz pulses from 00 to 59 and sends one pulse per minute to the minutes section. It is a mod-60 counter made of a mod-10 (units) counter followed by a mod-6 (tens) counter, with decoders and displays.

Block diagram

 1 Hz pulses (from ÷50 divider of 50 Hz mains)
      |
      v
 +-----------+  Q3 (falls 9->0)  +-----------+
 | MOD-10    |------------------>| MOD-6     |--> 1 pulse
 | units     |                   | tens      |   per minute
 | (7490)    |                   | (reset at |   to minutes
 +-----------+                   |  0110)    |
   | | | |  BCD                  +-----------+
 +-----------+                     | | |
 | 7447      |                   +-----------+
 | decoder   |                   | 7447      |
 +-----------+                   +-----------+
   |a..g                           |a..g
 [7-seg units]                   [7-seg tens]

Working principle

1. 1 Hz input: the 50 Hz mains is shaped into pulses and divided by 50 (÷10 then ÷5) to give 1 pulse per second.
2. Units counter (mod-10): a decade counter such as 7490 counts 0, 1, …, 9 on successive seconds. On the 10th pulse it returns to 0; at this moment its MSB $Q_3$ goes from 1 to 0.
3. Tens counter (mod-6): the falling edge of the units $Q_3$ clocks the tens counter, so it advances once every 10 seconds: 0, 1, …, 5. It is a 3-bit ripple counter reset at 6 (0110) by a NAND gate of $Q_2$ and $Q_1$ (or a 7492 wired as ÷6).
4. Carry to minutes: when the display shows 59 and the next pulse arrives, units go 9 → 0 and tens go 5 → 6 → 0. The falling of the tens counter's $Q_2$ at this reset gives one pulse per minute, which clocks the minutes units counter.
5. Decoding and display: each counter's BCD outputs drive a BCD-to-7-segment decoder/driver (7447 for common-anode displays). The decoder lights segments a–g to show the digit, so the seconds read 00, 01, …, 59, 00.

Count sequence

The minutes section is built exactly the same way; only the hours section uses different (mod-12 or mod-24) logic.

Synchronous vs asynchronous sequential circuits

Mod-12 synchronous counter

It counts 0000 to 1011 (0–11) and returns to 0000. Four JK flip-flops share a common clock; states 1100–1111 are don't cares.

Excitation table

Equations (from K-maps)

$$\begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_1Q_0 \\ &J_2 = \overline{Q_3}Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

Circuit diagram

   +-----+       +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2 J3>|J   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
K0>|K    |    K1>|K    |    K2>|K    |    K3>|K    |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
J0 = K0 = 1            J1 = K1 = Q0
J2 = Q3'.Q1.Q0  K2 = Q1.Q0
J3 = Q2.Q1.Q0   K3 = Q1.Q0

Operation

• $Q_0$ toggles on every clock edge.
• $Q_1$ toggles whenever $Q_0 = 1$.
• $Q_2$ sets when $Q_1Q_0 = 1$ and $Q_3 = 0$ (at 3 → 4), and resets when $Q_1Q_0 = 1$ (at 7 → 8). At 11 (1011), $Q_3 = 1$ blocks $J_2$, so $Q_2$ stays 0.
• $Q_3$ sets at 7 → 8 ($Q_2Q_1Q_0 = 1$) and resets at 11 → 0 ($Q_1Q_0 = 1$ with $Q_3 = 1$).
• So at the 12th clock, 1011 goes directly to 0000 with no false intermediate state.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   10  11  0

$Q_3$ is high for counts 8–11, giving $f_{clk}/12$. Unused states go 1100 → 1101 → 1110 → 1111 → 0000, so the counter is self-starting.