Transistor

In the common emitter (CE) configuration the emitter is common to input and output: input is between base and emitter (V_BE, I_B) and output is between collector and emitter (V_CE, I_C).

          RC
   +-----/\/\---+--- +VCC
   |            |C
 I_B   RB     |/
 o--/\/\----|      npn
            |\
              |E
             GND

Input characteristics (I_B vs V_BE, at constant V_CE)

 I_B |        /  /  V_CE = 1 V, 10 V
 (µA)|       /  /
     |      /  /
     |_____/__/________ V_BE
     0    0.7 V

• Similar to a forward-biased diode curve: almost no I_B until V_BE ≈ 0.7 V (Si), then I_B rises sharply.
• Increasing V_CE shifts the curve slightly to the right (less I_B for the same V_BE) due to base-width modulation (Early effect).
• Input resistance r_i = ΔV_BE/ΔI_B is low (about 1 kΩ).

Output characteristics (I_C vs V_CE, at constant I_B)

 I_C |  sat  _______________ I_B=40µA
 (mA)|   |  /_______________ I_B=30µA
     |   | /________________ I_B=20µA
     |   |/_________________ I_B=10µA
     |___/__________________ I_B=0 (cutoff)
     0  0.2V           V_CE

• For each I_B, I_C rises quickly for small V_CE and then becomes nearly flat: I_C ≈ β I_B.
• The slight upward slope is again due to the Early effect.

Regions of operation

The active region is the flat part of the curves, the saturation region is the steep part near the I_C axis (V_CE < about 0.2–0.3 V), and the cutoff region lies below the I_B = 0 curve. CE gives both current and voltage gain, so it is the most widely used amplifier configuration.

For DC analysis the capacitors are open circuits; the bypass capacitor CE does not affect the DC values, so RE = 1 kΩ is in the emitter circuit. Take V_BE = 0.7 V (Si).

Q point

Base loop (KVL): VCC − I_B RB − V_BE − I_E RE = 0 with I_E = (β + 1) I_B:

I_B = (VCC − V_BE)/(RB + (β + 1) RE)
    = (20 − 0.7)/(430 k + 51 × 1 k)
    = 19.3/481 k
    = 40.12 µA
I_C = β I_B = 50 × 40.12 µA = 2.006 mA
I_E = (β + 1) I_B = 2.046 mA

Collector loop:

V_CE = VCC − I_C RC − I_E RE
     = 20 − 2.006 × 2 − 2.046 × 1
     = 13.94 V

(Taking I_E ≈ I_C: V_CE ≈ 20 − 2.006 × 3 ≈ 13.98 V.)

Q point: I_CQ ≈ 2.01 mA, V_CEQ ≈ 13.94 V (I_BQ ≈ 40.1 µA).

DC load line

Equation (I_E ≈ I_C): V_CE = VCC − I_C (RC + RE)

I_C = 0       → V_CE(cutoff) = VCC = 20 V
V_CE = 0      → I_C(sat) = 20/(2 k + 1 k) = 6.67 mA

 I_C (mA)
 6.67 *
      | \
      |   \
 2.01 |- - -Q
      |      : \
      |      :   \
    0 +------:-----*----- V_CE (V)
      0    13.94   20

Region of operation

V_CE = 13.94 V is well above V_CE(sat) ≈ 0.2 V and I_C = 2.01 mA is well below I_C(sat) = 6.67 mA. The base-emitter junction is forward biased and the base-collector junction is reverse biased (V_C = 20 − 2.006 × 2 = 15.99 V > V_B = 2.75 V).

Answer: the transistor operates in the active region, near the middle of the load line, suitable for amplification.

An n-channel enhancement MOSFET (E-MOSFET) is a field-effect transistor in which no channel exists at V_GS = 0; a channel is created ("enhanced") only when a positive gate voltage above the threshold V_T is applied.

Construction

        S        G        D
        |      __|__      |
     ___|___  |metal|  ___|___
    |  n+   ||=SiO2=||  n+   |
    |_______|  ~~~~  |_______|
    |      induced n-channel   |
    |      p-type substrate    |
    |__________________________|
                 |
             SS (body)

• A lightly doped p-type substrate forms the body.
• Two heavily doped n+ regions are diffused into it to form the source and drain.
• A thin layer of silicon dioxide (SiO₂) insulates the substrate surface; a metal (or polysilicon) gate is placed on top. The gate is insulated, so gate current is practically zero (very high input resistance, about 10¹⁰–10¹⁵ Ω).
• There is no built-in channel between source and drain. The substrate is usually connected to the source.

Working principle

1. V_GS = 0: source and drain are separated by p-type material, forming two back-to-back pn junctions. Only a tiny leakage current flows, so I_D ≈ 0 (device OFF).
2. 0 < V_GS < V_T: the positive gate repels holes from the region under the oxide, leaving a depletion region of negative ions. Still no conduction.
3. V_GS ≥ V_T (threshold, typically 1–3 V): enough electrons (minority carriers of the p-substrate) are attracted under the gate to form a thin n-type inversion layer. This channel connects source and drain, and with V_DS > 0, electrons flow from source to drain: I_D flows.
4. Larger V_GS → thicker channel → larger I_D. Hence the name "enhancement".
5. Effect of V_DS: as V_DS increases, the channel near the drain narrows. When V_DS ≥ V_GS − V_T, the channel is pinched off at the drain end and I_D saturates.

In saturation: I_D = k (V_GS − V_T)², valid for V_GS > V_T.

 I_D |            ______ V_GS = 6 V
     |          _/______ V_GS = 5 V
     |        _/________ V_GS = 4 V
     |_______/__________ V_GS ≤ V_T
     0               V_DS

E-MOSFETs are used as switches in digital ICs (CMOS) because they are normally OFF.

Given: VCC = 20 V, RC = 2 kΩ, R1 = 20 kΩ, R2 = 10 kΩ, RE = 4 kΩ, β = 100, V_BE = 0.7 V (Si).

 VCC=20V --+---------+
           |         |
          R1=20k    RC=2k
           |         |C
   B ------+-------|/
           |       |\  β=100
          R2=10k     |E
           |        RE=4k
 GND ------+---------+

Check for approximate analysis

βRE = 100 × 4 kΩ = 400 kΩ ≥ 10 R2 = 100 kΩ, so the approximate method is valid.

Q point (approximate method)

V_B  = VCC × R2/(R1 + R2) = 20 × 10/30 = 6.667 V
V_E  = V_B − V_BE = 6.667 − 0.7       = 5.967 V
I_E  = V_E/RE = 5.967/4 k            = 1.492 mA
I_C  ≈ I_E                            = 1.492 mA
V_CE = VCC − I_C (RC + RE)
     = 20 − 1.492 × (2 + 4)           = 11.05 V
I_B  = I_C/β = 14.9 µA

Check with the exact (Thevenin) method:

R_Th = R1 || R2 = 20 k × 10 k/30 k = 6.667 kΩ
I_B  = (6.667 − 0.7)/(6.667 k + 101 × 4 k) = 14.53 µA
I_C  = 100 × 14.53 µA = 1.453 mA
V_CE = 20 − 1.453 × 2 − 1.468 × 4 = 11.22 V

Q point: I_CQ ≈ 1.49 mA, V_CEQ ≈ 11.05 V (exact: 1.45 mA, 11.22 V).

DC load line

V_CE = VCC − I_C (RC + RE):

I_C = 0    → V_CE = 20 V            (cutoff point)
V_CE = 0   → I_C(sat) = 20/6 k = 3.33 mA (saturation point)

 I_C (mA)
 3.33 *
      |  \
      |    \
 1.49 |- - - Q
      |      :  \
    0 +------:----*---- V_CE (V)
      0    11.05  20

The Q point lies near the middle of the load line, so the transistor operates in the active region and allows a large undistorted output swing.

A BJT works as an electronic switch when it is driven between cutoff (switch OFF) and saturation (switch ON), never staying in the active region.

Circuit

              +VCC
               |
              RC (load, e.g. lamp/relay)
               |
               +------ Vout
               |C
 Vin --[RB]--|/   npn
             |\
               |E
              GND

Operation

Switch OFF (cutoff): Vin = 0 V (logic 0). V_BE < 0.7 V, so I_B = 0 and I_C ≈ 0. No current flows through RC, so Vout = VCC. Collector–emitter acts like an open switch.

Switch ON (saturation): Vin = high (e.g. 5 V). Base current I_B = (Vin − 0.7)/RB is made large enough that the transistor saturates:

I_C(sat) = (VCC − V_CE(sat))/RC ≈ VCC/RC
Condition: I_B ≥ I_C(sat)/β  (use 2-5 times for safety)

Then V_CE = V_CE(sat) ≈ 0.2 V, so Vout ≈ 0. Collector–emitter acts like a closed switch and the load gets nearly full VCC.

Example: VCC = 5 V, RC = 1 kΩ, β = 100: I_C(sat) ≈ 5 mA, I_B(min) = 50 µA. With Vin = 5 V, RB = 10 kΩ gives I_B = 0.43 mA, which ensures saturation.

The circuit is also a logic inverter (high input → low output). It has very small power loss in both states, since either I_C ≈ 0 or V_CE ≈ 0. Uses: driving relays, LEDs, lamps and digital logic.

An n-channel depletion MOSFET (D-MOSFET) has a channel built in during manufacture, so drain current flows even at V_GS = 0. It can work in two modes: depletion mode (V_GS negative) and enhancement mode (V_GS positive).

Construction

        S        G        D
        |      __|__      |
     ___|___  |metal|  ___|___
    |  n+   ||=SiO2=||  n+   |
    |_______|________|_______|
    |   diffused n-channel     |
    |                          |
    |    p-type substrate      |
    |__________________________|
                 |
             SS (body, tied to S)

• A lightly doped p-type substrate forms the body.
• Two heavily doped n+ regions form the source and drain.
• A thin n-type channel is diffused between them, linking source and drain.
• A thin SiO₂ layer insulates the metal gate from the channel, so gate current ≈ 0 and input resistance is very high.

Operation

1. V_GS = 0: with a positive V_DS, electrons flow from source to drain through the existing n-channel. The current at V_GS = 0 with the channel pinched off is I_DSS.

2. V_GS negative (depletion mode): the negative gate repels electrons from the channel and attracts holes from the p-substrate, which recombine with electrons. The number of free electrons in the channel falls (the channel is depleted), so I_D decreases. At V_GS = V_P (pinch-off voltage, e.g. −4 V) the channel is fully depleted and I_D = 0.

3. V_GS positive (enhancement mode): the positive gate attracts more electrons (minority carriers) from the substrate into the channel. The channel becomes richer in carriers and I_D rises above I_DSS. This is possible because the gate is insulated, so no gate current flows. (A JFET cannot do this.)

4. Effect of V_DS: as V_DS rises, the channel narrows near the drain because the gate-to-drain voltage becomes more negative. At V_DS = V_GS − V_P the channel pinches off at the drain end, and I_D becomes nearly constant (saturation).

Characteristics

In saturation the transfer characteristic follows Shockley's equation: I_D = I_DSS (1 − V_GS/V_P)².

 Transfer             Drain
 I_D                  I_D |   ______ +1 V (enh.)
  |       /               |  /______ 0 V  (I_DSS)
  |      /                | /_______ −1 V
 I_DSS  *                 |/________ −2 V (depl.)
  |   /                   +------------- V_DS
  |_/______ V_GS
 V_P   0   +

 Symbol (n-channel D-MOSFET):
           D
           |
     G ||--+   solid line =
       ||<-+-- SS   built-in channel
       ||--+
           S

Summary

D-MOSFETs are used in RF amplifiers and as constant-current loads because they conduct at zero bias and accept both polarities of gate voltage.