Applications

A frequency counter measures the frequency of a signal by counting the number of its cycles during an accurately known time interval (the gate time) and displaying the count:

$$f = \frac{N}{T_{gate}}$$

Block diagram

 Input   +-----------+  pulses  +-----+   +-----------+
 signal->| Amplifier |--------->|     |-->| Decade    |
         | & Schmitt |          | AND |   | counters  |
         | trigger   |    +---->|gate |   | (BCD)     |
         +-----------+    |     +-----+   +-----+-----+
                          |                     |
 +---------+  +---------+ | gate     +----------v----+
 | Crystal |->| Divider |-+ pulse    | Latch         |
 | osc.    |  | chain   |---+        +-------+-------+
 +---------+  +---------+   |                |
                       +----v-----+  +-------v-------+
                       | Control  |  | BCD to 7-seg  |
                       | (reset,  |  | decoders and  |
                       |  latch)  |  | displays      |
                       +----------+  +---------------+

Working of each block

1. Amplifier and Schmitt trigger (wave shaper): amplifies the unknown input (sine, triangle, etc.) and converts it into clean rectangular pulses of the same frequency, one pulse per cycle.
2. Time base: a crystal oscillator (e.g. 1 MHz) followed by a chain of divide-by-10 counters gives a very accurate gate pulse of 1 s, 0.1 s, 10 ms, … selected by the range switch.
3. AND (main) gate: one input receives the shaped pulses, the other the gate pulse. Pulses pass to the counter only while the gate pulse is HIGH, i.e. for exactly $T_{gate}$.
4. Decade counters: cascaded BCD counters (e.g. 7490) count the pulses that pass the gate; each counter is one decimal digit.
5. Control logic: before each gate period it resets the counters; when the gate closes it sends a latch (transfer) pulse, then resets again for the next measurement.
6. Latch, decoder and display: the latch holds the final count so the display does not flicker while counting; BCD-to-7-segment decoders (e.g. 7447) drive the LED displays.

Example

With $T_{gate} = 1$ s, if 5000 pulses pass the gate, $f = 5000 / 1 = 5000$ Hz = 5 kHz. With a 0.1 s gate the same signal gives 500 counts, displayed as 5.00 kHz with the decimal point shifted. A longer gate gives better resolution (1 Hz for a 1 s gate); the accuracy depends on the crystal time base, with an error of ±1 count.

A multiplexed display drives several 7-segment digits by sharing one set of segment lines (a–g) and one BCD-to-7-segment decoder among all digits, and switching the digits on one at a time in rapid sequence. Because each digit is refreshed faster than the eye can follow (persistence of vision), all digits appear to be lit continuously.

Need for multiplexing

• A non-multiplexed 4-digit display needs 4 decoders and $4 \times 7 = 28$ segment lines.
• A multiplexed display needs only 1 decoder, 7 segment lines and 4 digit-select lines (11 lines in total).
• Fewer ICs, less wiring, lower power (only one digit draws current at a time).

Block diagram

 BCD digit 0 ─┐
 BCD digit 1 ─┤ 4-bit    BCD  BCD-to-7  a..g
 BCD digit 2 ─┤ 4:1 MUX ────> segment ─────┬──┬──┬──┐
 BCD digit 3 ─┘ (x4)          decoder      │  │  │  │
                  ^                       [D3][D2][D1][D0]
                  │ S1 S0                  ^   ^   ^   ^
 Clock ─> 2-bit ──┴──> 2-to-4 decoder ─────┴───┴───┴───┘
 (~1 kHz) counter      (one digit enabled at a time)

The segment lines a–g of all four displays are wired in parallel. Each display's common cathode (or common anode) is driven separately through a transistor by one output of the 2-to-4 decoder.

Operation

1. A clock (typically 100 Hz – 1 kHz) drives a 2-bit counter that cycles 00, 01, 10, 11.
2. The counter output selects one BCD digit through the data multiplexer and sends it to the single BCD-to-7-segment decoder.
3. The same counter output goes to a 2-to-4 decoder, which enables only the matching display (e.g. count 00 turns on D0).
4. So during the first time slot, digit 0's code appears on the segment lines and only D0 glows; in the next slot digit 1's code appears and only D1 glows, and so on.
5. Each digit is ON for 1/4 of the cycle (duty cycle 25%). If the full scan repeats at more than about 50 times per second, no flicker is seen.
6. Since each digit is ON only part of the time, a higher peak current is given to keep the brightness the same.

Example

To show 2025: in slot 0 the code for 5 is sent and D0 lights; slot 1 sends 2 to D1; slot 2 sends 0 to D2; slot 3 sends 2 to D3. Scanning at 1 kHz gives each digit 250 refreshes per second, so the eye sees "2025" steadily.

Multiplexed displays are used in digital clocks, frequency counters, calculators and digital meters.

A time measurement circuit (digital timer / period meter) measures the time interval between two events by counting pulses of a known, accurate clock during that interval. If a clock of period $T_c$ gives $N$ counts, the measured time is $t = N \times T_c$.

Block diagram

 Start ──> ┌──────┐
           │ S-R  │ Q = gate
 Stop  ──> │  FF  │─────────┐
           └──────┘         v
 Crystal ─> Time-base ─> ┌─────┐
 oscillator divider      │ AND │
                         └──┬──┘
                            v
 Reset ─────────────> ┌──────────────┐
                      │Decade counter│
                      └──────┬───────┘
                             v
                      ┌──────────────┐
                      │    Latch     │
                      └──────┬───────┘
                             v
                      ┌──────────────┐
                      │BCD-to-7-seg  │
                      │dec. + display│
                      └──────────────┘

Blocks

1. Crystal oscillator – generates a very stable frequency (e.g. 1 MHz).
2. Time-base divider – chain of decade counters (÷10 stages) giving selectable clock periods such as 1 µs, 10 µs, 1 ms. This sets the resolution of the reading.
3. Start/stop control (S-R flip-flop) – the start pulse sets the flip-flop ($Q = 1$); the stop pulse resets it ($Q = 0$). So $Q$ is HIGH exactly for the time interval to be measured.
4. AND gate (main gate) – passes time-base clock pulses to the counter only while $Q = 1$.
5. Decade (BCD) counters – count the pulses passed by the gate.
6. Latch, decoder and display – the latch holds the final count; BCD-to-7-segment decoders show it on the display (usually multiplexed).

Operation

1. Before measurement the counters are reset to zero.
2. The start event sets the flip-flop, opening the AND gate. Clock pulses enter the counter.
3. The stop event resets the flip-flop, closing the gate. Counting stops.
4. The count $N$ is latched and displayed; the time is $t = N \times T_c$, so the display reads directly in µs or ms depending on the selected time base.

Example

With a 1 ms time base, if 2,350 pulses pass the gate, then

$$t = 2350 \times 1\ \text{ms} = 2.35\ \text{s}$$

Period measurement

For measuring the period of a signal, the input is shaped into pulses and applied to a toggle (divide-by-2) flip-flop; its output stays HIGH for exactly one period and acts as the gate. The accuracy is $\pm 1$ count plus the accuracy of the crystal.

BCD-to-7-segment decoder

A BCD-to-7-segment decoder is a combinational circuit that converts a 4-bit BCD input (DCBA = 0000 to 1001) into the seven outputs a–g needed to light the segments of a 7-segment display, so that the decimal digit 0–9 appears. Example: input 0101 (5) makes segments a, f, g, c, d active. The 7447 (active-LOW outputs, for common-anode displays) and 7448 (active-HIGH, for common-cathode) are common ICs.

       a
     ─────
  f |     | b       DCBA ─> [7447] ─> a b c d e f g
    |  g  |
     ─────
  e |     | c
    |     |
     ─────
       d

Frequency counter

A frequency counter measures the frequency of a signal by counting how many cycles of the signal occur during an accurately known gate time. If $N$ cycles are counted in gate time $T_g$:

$$f = \frac{N}{T_g}$$

With $T_g = 1$ s, the count $N$ is directly the frequency in Hz.

 Input ─> Amplifier + Schmitt ──────┐
                                    v
 Crystal ─> Time-base ─> Gate ─> ┌─────┐
 osc.       divider     control  │ AND │
                          │  │   └──┬──┘
                          │  │      v
                          │  └─> Decade counters
                          │   reset    │
                          │            v
                          └──────> Latch (strobe)
                                       v
                             BCD-to-7-seg decoders
                                       v
                               7-segment display

Blocks and operation

1. Input shaper – an amplifier and Schmitt trigger convert the unknown input (sine, triangle, etc.) into clean rectangular pulses, one per cycle.
2. Crystal oscillator and time-base divider – a stable oscillator (e.g. 1 MHz) is divided by decade counters to give accurate gate times such as 1 s, 0.1 s or 10 ms.
3. Gate control flip-flop – produces a gate pulse of exactly $T_g$ width.
4. Main AND gate – passes input pulses to the counters only during $T_g$.
5. Decade counters (e.g. 7490) – count the pulses in BCD.
6. Latch – at the end of the gate time a strobe pulse copies the count into the latch so the display stays steady; then a reset pulse clears the counters for the next measurement.
7. BCD-to-7-segment decoders and display – show the latched count, usually as a multiplexed display.

Example: with $T_g = 0.1$ s, if 4,567 pulses are counted, $f = 4567 / 0.1 = 45{,}670$ Hz $= 45.67$ kHz.

A longer gate time gives better resolution ($\pm 1$ count $= \pm 1/T_g$ Hz) but a slower update.

Applications of digital devices

Digital ICs (gates, flip-flops, counters, registers, decoders, multiplexers) are used wherever information is processed as binary signals:

• Computers and microprocessors – arithmetic, memory, control units.
• Digital instruments – frequency counters, digital voltmeters and multimeters, time-interval meters.
• Digital clocks and timers, stopwatches, multiplexed displays.
• Communication – multiplexing, encoding/decoding, error detection (parity), digital switching.
• Control systems – traffic light controllers, vending machines, industrial PLCs.
• Consumer products – calculators, mobile phones, digital TV and cameras.

Frequency counter

A frequency counter counts the number of cycles of an input signal during a precise gate time $T_g$; then $f = N / T_g$. With $T_g = 1$ s the count equals the frequency in Hz.

 Input ─> Schmitt ─> ┌─────┐   ┌─────────┐
          trigger    │ AND │─> │ Decade  │
                     └─────┘   │counters │
                        ^      └────┬────┘
 Crystal ─> Divider ─> gate         v
 (1 s gate, latch/reset)  Latch ─> Decoder ─> Display

Operation

1. The Schmitt trigger shapes the input into one clean pulse per cycle.
2. A crystal oscillator and divider chain give an accurate gate pulse (e.g. 1 s).
3. The AND gate lets input pulses reach the decade counters only during the gate time.
4. At the end of the gate, the count is transferred to the latch and shown through BCD-to-7-segment decoders; the counters are then reset for the next reading.

Example: 50,000 pulses counted in a 1 s gate means $f = 50$ kHz.