Digital Integrated Circuits

TTL signal levels are the guaranteed voltage ranges that a standard TTL (74xx) gate, with $V_{CC} = 5\ \text{V}$, accepts at its input and produces at its output as logic 0 and logic 1.

 Output side           Input side
 5.0 +-----+           5.0 +-----+
     | HIGH|               | HIGH|
 2.4 +-----+  ------>  2.0 +-----+
     | bad |               |indet|
 0.4 +-----+  ------>  0.8 +-----+
     | LOW |               | LOW |
 0   +-----+           0   +-----+

Input voltages between 0.8 V and 2.0 V are indeterminate and must be avoided. The difference between output and input limits gives the noise margin:

$$\begin{aligned} NM_H &= V_{OH(min)} - V_{IH(min)} = 2.4 - 2.0 = 0.4\ \text{V} \\ NM_L &= V_{IL(max)} - V_{OL(max)} = 0.8 - 0.4 = 0.4\ \text{V} \end{aligned}$$

Example: a 7400 output at logic 0 is at most 0.4 V. Even if 0.3 V of noise is added on the wire, the next gate sees 0.7 V, which is still below 0.8 V and is read as logic 0.

Propagation delay

Propagation delay is the time between a change at a gate's input and the resulting change at its output, measured between the 50% points of the input and output edges.

• $t_{PHL}$: delay when the output goes from HIGH to LOW.
• $t_{PLH}$: delay when the output goes from LOW to HIGH.
• Average delay: $t_{pd} = \dfrac{t_{PHL} + t_{PLH}}{2}$.

 In   ____/--------\______
          50%      50%
 Out  -------\________/----
          |<->|    |<->|
          tPHL     tPLH

It limits the maximum operating speed (typical: about 10 ns for 74LS TTL, about 8–10 ns for 74HC CMOS).

3-input CMOS NOR gate

It uses 3 PMOS transistors in series between $V_{DD}$ and the output (pull-up network) and 3 NMOS transistors in parallel between the output and ground (pull-down network). Each input A, B, C drives the gates of one PMOS and one NMOS.

          VDD
           |
    A --o| P1
           |
    B --o| P2
           |
    C --o| P3
           |
           +------------- Y = (A+B+C)'
           |       |       |
    A --| N1  B --| N2  C --| N3
           |       |       |
          GND     GND     GND

Operation:

• All inputs 0: all three PMOS are ON (gate low) and all NMOS are OFF. The series PMOS chain connects Y to $V_{DD}$, so Y = 1.
• Any input 1: that input's NMOS turns ON and pulls Y to ground, and its PMOS turns OFF, breaking the pull-up chain. So Y = 0.
• In every case only one network conducts, so no steady current flows from $V_{DD}$ to ground: static power is almost zero.

Hence $Y = \overline{A + B + C}$.

Characteristics of CMOS gates

CMOS (complementary MOS) gates use PMOS pull-up and NMOS pull-down transistors in pairs. Main characteristics (4000B and 74HC series):

2-input CMOS NOR gate

Two PMOS transistors $P_1$, $P_2$ are in series from $V_{DD}$ to the output, and two NMOS transistors $N_1$, $N_2$ are in parallel from the output to ground. Input A drives $P_1$ and $N_1$; input B drives $P_2$ and $N_2$.

            VDD
             |
     A --o| P1
             |
     B --o| P2
             |
             +---------- Y = (A+B)'
             |        |
     A ---| N1  B ---| N2
             |        |
            GND      GND

A PMOS is ON when its gate is 0; an NMOS is ON when its gate is 1.

Operation:

• A = 0, B = 0: $P_1$, $P_2$ ON; $N_1$, $N_2$ OFF. Output connected to $V_{DD}$ → Y = 1.
• A = 0, B = 1: $N_2$ ON pulls output to ground; $P_2$ OFF breaks the pull-up path → Y = 0.
• A = 1, B = 0: $N_1$ ON, $P_1$ OFF → Y = 0.
• A = 1, B = 1: both NMOS ON, both PMOS OFF → Y = 0.

So $Y = \overline{A + B}$. Since the pull-up and pull-down networks are never ON together in steady state, no DC path exists from $V_{DD}$ to ground, which is why CMOS static power is so low.

Propagation delay time

Propagation delay is the time a gate's output takes to respond to a change at its input, measured from the 50% point of the input edge to the 50% point of the output edge.

• $t_{PHL}$: input change to output going HIGH → LOW.
• $t_{PLH}$: input change to output going LOW → HIGH.
• Average: $t_{pd} = \dfrac{t_{PHL} + t_{PLH}}{2}$. For standard 7400 TTL, $t_{PLH} \approx 11$ ns and $t_{PHL} \approx 7$ ns, so $t_{pd} \approx 9$ ns.

 In   ____/--------\_______
          :         :
 Out  -----:-\_______:-/----
          |<>|      |<>|
          tPHL      tPLH

Smaller delay means a faster gate (higher maximum frequency).

2-input TTL NAND gate

A TTL NAND gate (7400) is built with bipolar transistors: a multi-emitter input transistor, a phase splitter and a totem-pole output.

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Circuit parts (standard 7400):

• Q1 (multi-emitter input transistor): one emitter per input; works like an AND of diodes.
• Q2 (phase splitter): gives opposite signals at its collector and emitter to drive the output pair.
• Q3, D1, Q4 (totem-pole output): Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching.

Operation:

• Any input LOW (≈ 0.2 V): that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to turn on the Q1 base–collector junction plus Q2 and Q4 (needs about 1.4 V), so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, so Q3 conducts as an emitter follower and the output is HIGH (about 3.4 V with no load, at least 2.4 V guaranteed).
• All inputs HIGH: all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2, so Q2 and Q4 saturate. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so Q3 is OFF.

Hence $Y = \overline{AB}$.

TTL NOR gate

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

CMOS characteristics

CMOS characteristics:

• Very low static power (nW per gate), since the PMOS and NMOS networks are never ON together; dynamic power $P_D = C_L V_{DD}^2 f$ rises with frequency.
• Wide supply range: 3–15 V for 4000B, 2–6 V for 74HC.
• High noise margin: about 30% of $V_{DD}$ (≈ 1.4 V at 5 V); output swings almost rail to rail (≈ 0 V to $V_{DD}$).
• High fan-out (about 50), as MOS inputs draw almost no current.
• Speed: 74HC about 8–10 ns delay (similar to LS TTL); 4000B slower (25–100 ns).
• Static sensitive: inputs must be protected and never left floating.

CMOS parameters

The main parameters of a CMOS gate (typical 5 V values):

• Supply voltage $V_{DD}$: 3–15 V (4000B), 2–6 V (74HC).
• Input levels: $V_{IH(min)} \approx 3.5$ V (70% of $V_{DD}$), $V_{IL(max)} \approx 1.5$ V (30% of $V_{DD}$).
• Output levels: $V_{OH(min)} \approx 4.9$ V, $V_{OL(max)} \approx 0.1$ V (almost rail to rail).
• Noise margin: $NM_H = 4.9 - 3.5 = 1.4$ V, $NM_L = 1.5 - 0.1 = 1.4$ V.
• Power dissipation: nearly zero when static; dynamic $P_D = C_L V_{DD}^2 f$.
• Propagation delay: about 8–10 ns (74HC), 25–100 ns (4000B).
• Fan-out: about 50, limited by input capacitance, not by current.

2-input CMOS NAND gate

          VDD               VDD
           |                 |
    A --o| P1        B --o| P2
           |                 |
           +--------+--------+
                    |
                    +------------ Y = (AB)'
                    |
             A --| N1
                    |
             B --| N2
                    |
                   GND

(P = PMOS, ON when gate = 0; N = NMOS, ON when gate = 1.)

The two PMOS transistors are in parallel between $V_{DD}$ and the output; the two NMOS transistors are in series between the output and ground.

• A = 0 or B = 0: at least one PMOS is ON, connecting Y to $V_{DD}$, and the series NMOS path is broken → Y = 1.
• A = 1 and B = 1: both NMOS are ON, connecting Y to ground; both PMOS are OFF → Y = 0.

So $Y = \overline{AB}$. In no input state are both networks ON, so no DC current flows from $V_{DD}$ to ground.

A 3-input TTL NAND gate (7410) is the same as the standard TTL NAND circuit, but the input transistor Q1 has three emitters, one for each input A, B, C.

              +5 V
   +-----------+----------+
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
C--e        +--b Q2       |
               e         D1
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

Operation

• Any input LOW: that emitter junction of Q1 is forward biased and Q1's base is held at about 0.9 V. No current reaches Q2's base, so Q2 and Q4 are OFF. Q2's collector is high (through R2), so Q3 is ON and the output is HIGH (≈ 3.4 V, ≥ 2.4 V guaranteed).
• All inputs HIGH: all three emitter junctions are reverse biased. R1 current flows through Q1's base–collector junction into Q2, so Q2 and Q4 saturate and the output is LOW (≈ 0.2 V). Q2's collector is about 0.9 V, too low to turn on Q3 and D1, so Q3 is OFF.

So $Y = \overline{ABC}$.

Significance of the totem-pole output

• Q3 (pull-up) and Q4 (pull-down) are stacked; only one is ON at a time. Q3 actively sources current for a HIGH output, Q4 sinks current for a LOW output.
• Both states have low output resistance, so the load capacitance charges and discharges quickly: fast switching and good fan-out (10).
• Lower power than a resistor pull-up, since no resistor current flows in the LOW state.
• D1 keeps Q3 OFF when Q4 is ON; R4 (130 Ω) limits the current spike when both conduct for an instant during switching.
• Drawback: totem-pole outputs cannot be tied together (wired-AND), as a HIGH output shorted to a LOW one draws heavy current.

The CMOS logic level profile shows the voltage ranges for logic 0 and 1 at the output and at the input of a CMOS gate. Typical values for $V_{DD} = 5$ V:

  Output                 Input
 5.0 +--------+         5.0 +--------+
     | HIGH   |             | HIGH   |
 4.9 +--------+ VOH(min)    |        |
     |        |  NM_H=1.4   |        |
     |invalid |         3.5 +--------+ VIH(min)
     |        |             | indet. |
     |        |         1.5 +--------+ VIL(max)
     |        |  NM_L=1.4   | LOW    |
 0.1 +--------+ VOL(max)    |        |
     | LOW    |             |        |
 0.0 +--------+         0.0 +--------+

• Output: $V_{OH(min)} = 4.9$ V, $V_{OL(max)} = 0.1$ V (nearly $V_{DD}$ and 0 V, since MOS outputs drive almost no DC current).
• Input: $V_{IH(min)} = 3.5$ V (70% of $V_{DD}$), $V_{IL(max)} = 1.5$ V (30% of $V_{DD}$).
• Noise margins: $NM_H = 4.9 - 3.5 = 1.4$ V and $NM_L = 1.5 - 0.1 = 1.4$ V, much larger than TTL's 0.4 V.

A CMOS inverter is the basic CMOS gate: one PMOS and one NMOS enhancement MOSFET in series between $V_{DD}$ and ground, with their gates joined as the input and their drains joined as the output.

          VDD
           |
           s
   +---o| Q1 (PMOS)
   |       d
 A-+       +-------- Y = A'
   |       d
   +----| Q2 (NMOS)
           s
           |
          GND

Operation

• A = 0 (0 V): for the PMOS, $V_{GS} = -V_{DD}$, so Q1 is ON; for the NMOS, $V_{GS} = 0$, so Q2 is OFF. The output is connected to $V_{DD}$ through Q1's low ON resistance → Y = 1.
• A = 1 ($V_{DD}$): Q1 has $V_{GS} = 0$ → OFF; Q2 has $V_{GS} = V_{DD}$ → ON. The output is connected to ground → Y = 0.

Features

• In either steady state one transistor is OFF, so no DC current flows from $V_{DD}$ to ground: static power is almost zero. Current flows only briefly while switching and to charge the load capacitance ($P_D = C_L V_{DD}^2 f$).
• Output swings nearly from 0 to $V_{DD}$; the switching threshold is about $V_{DD}/2$, giving a high noise margin.
• Very high input resistance gives a large fan-out.

TTL NOR gate

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

Propagation delay

Propagation delay is the time between a change at a gate's input and the resulting change at its output, measured between the 50% points of the two edges. It has two values: $t_{PHL}$ (output falls) and $t_{PLH}$ (output rises); the average is $t_{pd} = (t_{PHL} + t_{PLH})/2$. For standard TTL (7400) $t_{pd} \approx 9$–10 ns. It sets the maximum speed of the gate.

Characteristics of CMOS logic families

CMOS (complementary MOS) logic uses a PMOS pull-up and an NMOS pull-down network in each gate. Its main characteristics:

TTL 2-input AND gate

A TTL AND gate (7408) is a NAND input stage followed by one more inverting stage and the totem-pole output, so the output is the complement of NAND.

 Input section (NAND stage):
             +5 V
   +----------+
 R1 4k      R2 4k
   |          |
   b          +------- X
A--e  Q1      |
B--e    c--+  c
           +--b Q2
              e
              |
            R4 1k
              |
             GND

 Output section (common to AND and OR):
              +5 V
          +------+------+
       R3 1.6k       R5 130
          |             |
          +------+      c
          |      +----b Q4
          c             e
 X -----b Q3            |
          e            D1
          |             |
          +------+      +----- Y
          |      |      c
        R6 1k    +----b Q5
          |             e
 GND -----+-------------+

Node X (collector of Q2) drives the base of Q3. Q1 = multi-emitter input, Q2 = NAND stage, Q3 = phase splitter, Q4–D1–Q5 = totem-pole output.

Operation:

• Any input LOW: Q1's base is held at about 0.9 V, so Q2 is OFF. Node X is pulled up by R2 and supplies base current to Q3, so Q3 turns ON, which turns Q5 ON and Q4 OFF → Y = 0.
• A = B = 1: Q1's base current goes into Q2, so Q2 saturates and pulls node X (Q3's base) LOW → Q3 OFF → Q5 OFF, Q4 ON → Y = 1.

So $Y = AB$. Because of the extra stage, a TTL AND gate has a slightly longer delay than a TTL NAND.

TTL two-input OR gate

A TTL OR gate (7432) is a NOR input section (two input transistors Q1A, Q1B with parallel stages Q2A, Q2B) followed by an extra inverting stage Q3 and a totem-pole output Q4–D1–Q5, so the output is the complement of NOR.

 Input section (NOR stage):
                 +5 V
   +-------+--------+
 R1A 4k  R1B 4k   R2 4k
   |       |        |
   b       b        +------- X
A--e Q1A B-e Q1B    |
   c       c     +--+--+
   |       |     c     c
   +-------)---b Q2A   |
           +---------b Q2B
                 e     e
                 +--+--+
                    |
                  R4 1k
                    |
                   GND

 Output section (common to AND and OR):
              +5 V
          +------+------+
       R3 1.6k       R5 130
          |             |
          +------+      c
          |      +----b Q4
          c             e
 X -----b Q3            |
          e            D1
          |             |
          +------+      +----- Y
          |      |      c
        R6 1k    +----b Q5
          |             e
 GND -----+-------------+

The joined collectors of Q2A and Q2B (node X) drive the base of Q3; the output section is the same as in a TTL AND gate.

Operation:

• A = B = 0: Q1A and Q1B conduct through their emitters, so Q2A and Q2B are OFF. Node X rises through R2 and turns Q3 ON; Q3 turns Q5 ON and Q4 OFF → Y = 0.
• A = 1 or B = 1: the corresponding Q2 saturates and pulls node X LOW → Q3 OFF → Q5 OFF, Q4 ON → Y = 1.

So $Y = A + B$.

Propagation delay time

The time between an input change and the resulting output change, measured at the 50% points: $t_{PHL}$ for a HIGH→LOW output and $t_{PLH}$ for LOW→HIGH; average $t_{pd} = (t_{PHL} + t_{PLH})/2$ (about 9–10 ns for standard TTL).

Power dissipation

The average power a gate takes from the supply:

$$P_D = V_{CC} \times I_{CC(avg)}, \qquad I_{CC(avg)} = \frac{I_{CCH} + I_{CCL}}{2}$$

For a 7400 package, $I_{CCH} = 4$ mA and $I_{CCL} = 12$ mA, so $I_{CC(avg)} = 8$ mA and $P_D = 5 \times 8 = 40$ mW per package, i.e. 10 mW per gate.

2-input TTL NAND gate

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Circuit parts (standard 7400):

• Q1 (multi-emitter input transistor): one emitter per input; works like an AND of diodes.
• Q2 (phase splitter): gives opposite signals at its collector and emitter to drive the output pair.
• Q3, D1, Q4 (totem-pole output): Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching.

Operation:

• Any input LOW (≈ 0.2 V): that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to turn on the Q1 base–collector junction plus Q2 and Q4 (needs about 1.4 V), so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, so Q3 conducts as an emitter follower and the output is HIGH (about 3.4 V with no load, at least 2.4 V guaranteed).
• All inputs HIGH: all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2, so Q2 and Q4 saturate. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so Q3 is OFF.

Hence $Y = \overline{AB}$.

CMOS characteristics

CMOS characteristics:

• Very low static power (nW per gate), since the PMOS and NMOS networks are never ON together; dynamic power $P_D = C_L V_{DD}^2 f$ rises with frequency.
• Wide supply range: 3–15 V for 4000B, 2–6 V for 74HC.
• High noise margin: about 30% of $V_{DD}$ (≈ 1.4 V at 5 V); output swings almost rail to rail (≈ 0 V to $V_{DD}$).
• High fan-out (about 50), as MOS inputs draw almost no current.
• Speed: 74HC about 8–10 ns delay (similar to LS TTL); 4000B slower (25–100 ns).
• Static sensitive: inputs must be protected and never left floating.

Voltage profile of TTL

The voltage profile of TTL ($V_{CC} = 5$ V) shows the voltage ranges that represent logic 0 and logic 1 at the output and at the input of a gate:

  Output (driving)       Input (receiving)
 5.0 +--------+         5.0 +--------+
     | HIGH   |             | HIGH   |
 2.4 +--------+ VOH(min) 2.0 +--------+ VIH(min)
     |invalid |  NM_H=0.4   | indet. |
 0.4 +--------+ VOL(max) 0.8 +--------+ VIL(max)
     | LOW    |  NM_L=0.4   | LOW    |
 0.0 +--------+         0.0 +--------+

• Output HIGH ≥ $V_{OH(min)} = 2.4$ V; output LOW ≤ $V_{OL(max)} = 0.4$ V.
• Input read as HIGH if ≥ $V_{IH(min)} = 2.0$ V; as LOW if ≤ $V_{IL(max)} = 0.8$ V; 0.8–2.0 V is indeterminate.
• Noise margins: $NM_H = 2.4 - 2.0 = 0.4$ V and $NM_L = 0.8 - 0.4 = 0.4$ V.

Tristate TTL inverter

A tristate (three-state) inverter has, besides the normal HIGH and LOW outputs, a third high-impedance (Hi-Z) state in which the output is effectively disconnected. It is used to connect many outputs to a common bus, with only one enabled at a time.

              +5 V
   +-----------+----------+
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
E--e     c--+  c     |    e
   |        +--b Q2  |   D1
   |           e     |    |
   |           +--+  |    +---- Y
   |           |  |  |    c
   |        R3 1k +--)--b Q4
   |           |     |    e
   |          GND   D2    |
   |                 |   GND
   +----- E line ----+

Q1 has a second emitter tied to the enable line E; diode D2 has its anode at Q3's base (Q2 collector) and its cathode on E.

Working:

• E = 1 (enabled): the second emitter of Q1 and diode D2 are reverse biased and have no effect. The circuit works as a normal TTL inverter: A = 0 → Q2, Q4 OFF, Q3 ON → Y = 1; A = 1 → Q2, Q4 ON, Q3 OFF → Y = 0.
• E = 0 (disabled): the E emitter of Q1 conducts, so Q2 and Q4 are OFF whatever A is. D2 also conducts and clamps Q3's base to about 0.9 V, which is not enough for Q3 and D1, so Q3 is OFF too. With both totem-pole transistors OFF the output floats: Hi-Z.

In ICs such as the 74125/74126 buffers the external enable pin may be active-LOW, with an internal inverter driving this E line.

A 3-input CMOS gate uses three PMOS–NMOS pairs. The 3-input CMOS NAND gate is shown: three PMOS in parallel from $V_{DD}$ to the output and three NMOS in series from the output to ground; each input drives one PMOS and one NMOS.

     VDD          VDD          VDD
      |            |            |
A --o| P1   B --o| P2   C --o| P3
      |            |            |
      +------------+------------+
                   |
                   +-------------- Y = (ABC)'
                   |
            A --| N1
                   |
            B --| N2
                   |
            C --| N3
                   |
                  GND

Operation

• A PMOS conducts when its gate is 0; an NMOS conducts when its gate is 1.
• Any input 0: the PMOS of that input is ON and connects Y to $V_{DD}$; the NMOS of that input is OFF, breaking the series path to ground → Y = 1.
• All inputs 1: all PMOS are OFF; all three series NMOS are ON and connect Y to ground → Y = 0.

So $Y = \overline{ABC}$. The pull-up and pull-down networks are never ON together, so static power is almost zero.

3-input NOR: swapping the arrangement (PMOS in series, NMOS in parallel) gives $Y = \overline{A + B + C}$: Y = 1 only when all inputs are 0.

TTL NAND gate

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Any input LOW → Q2, Q4 OFF, Q3 ON → Y = 1; all inputs HIGH → Q2, Q4 saturate, Q3 OFF → Y = 0. So $Y = \overline{AB}$.

Transistor as a switch

In digital circuits a BJT is operated only in two regions:

        +VCC
         |
         RC
         |
         +----- Vout
         c
 Vin-RB--b
         e
         |
        GND

So the transistor inverts: Vin LOW → OFF → Vout HIGH; Vin HIGH → saturated → Vout LOW.

Example: $V_{CC} = 5$ V, $R_C = 1\ \text{k}\Omega$, $\beta = 100$: $I_{C(sat)} = (5 - 0.2)/1\text{k} = 4.8$ mA, so the base current must be at least $4.8\ \text{mA}/100 = 48\ \mu$A for saturation. Switching speed is limited by the time needed to remove stored charge when leaving saturation (storage time).

TTL NOR gate

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

Totem pole

Totem-pole output is the TTL output stage in which two transistors are stacked one above the other between $V_{CC}$ and ground, like a totem pole: Q3 (active pull-up) on top with R4 = 130 Ω and diode D1, and Q4 (pull-down) below. The output Y is taken from their junction. The phase splitter Q2 drives them in opposite phase, so only one is ON at a time.

   +5 V
    |
  R4 130
    |
    c
Q2c-b Q3   (ON for HIGH output)
    e
    |
   D1
    +------- Y
    c
Q2e-b Q4   (ON for LOW output)
    e
    |
   GND

Significance:

• Low output resistance in both states: Q3 sources current and Q4 sinks current, so load capacitance is charged and discharged quickly → short rise and fall times, higher speed than a resistor pull-up.
• Low power: no resistor carries current continuously in the LOW state, unlike a passive pull-up.
• D1 gives an extra 0.7 V drop so Q3 is surely OFF when Q4 is saturated.
• R4 limits the current spike that flows for a few ns when both transistors are briefly ON during switching.
• Limitation: totem-pole outputs must not be wired together (wired-AND); if one output is HIGH and another LOW, a large current flows and may damage the gates. Open-collector or tristate outputs are used for bus connections.

A TTL inverter (7404) is the TTL NAND circuit with a single-emitter input transistor.

Schematic diagram

              +5 V
   +-----------+----------+
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
         c--+  c          e
            +--b Q2       |
               e         D1
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

• Q1: input transistor (base through R1 = 4 kΩ to $V_{CC}$).
• Q2: phase splitter (R2 = 1.6 kΩ collector, R3 = 1 kΩ emitter).
• Q3, D1, Q4: totem-pole output (R4 = 130 Ω).

Working principle

• A = 0 (≤ 0.8 V): Q1's base–emitter junction is forward biased; its base is at about 0.2 + 0.7 = 0.9 V. Turning on Q2 and Q4 needs about 1.4 V at Q1's base, so Q2 and Q4 stay OFF. Q2's collector is pulled up by R2, so Q3 is ON (emitter follower) and current flows from $V_{CC}$ through R4, Q3 and D1 to the load. Output Y ≈ 3.4 V (HIGH).
• A = 1 (≥ 2.0 V): Q1's emitter junction is reverse biased; R1 current flows through Q1's base–collector junction into Q2's base. Q2 saturates, its emitter current through R3 drives Q4 into saturation, and the output is pulled to $V_{CE(sat)} \approx 0.2$ V (LOW). Q2's collector is at about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1 (needs about 1.4 V above the 0.2 V output), so Q3 is OFF.

So $Y = \overline{A}$. The totem pole gives low output resistance in both states, so the gate switches quickly (≈ 10 ns) and can drive 10 standard TTL loads.

A TTL NAND gate (7400) is built with bipolar transistors: a multi-emitter input transistor, a phase splitter and a totem-pole output.

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Circuit parts (standard 7400):

• Q1 (multi-emitter input transistor): one emitter per input; works like an AND of diodes.
• Q2 (phase splitter): gives opposite signals at its collector and emitter to drive the output pair.
• Q3, D1, Q4 (totem-pole output): Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching.

Operation:

• Any input LOW (≈ 0.2 V): that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to turn on the Q1 base–collector junction plus Q2 and Q4 (needs about 1.4 V), so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, so Q3 conducts as an emitter follower and the output is HIGH (about 3.4 V with no load, at least 2.4 V guaranteed).
• All inputs HIGH: all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2, so Q2 and Q4 saturate. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so Q3 is OFF.

Hence $Y = \overline{AB}$.

Key values: $V_{OH} \approx 3.4$ V (≥ 2.4 V), $V_{OL} \approx 0.2$ V (≤ 0.4 V), propagation delay ≈ 10 ns, power ≈ 10 mW per gate, fan-out 10.

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

CMOS NAND gate

          VDD               VDD
           |                 |
    A --o| P1        B --o| P2
           |                 |
           +--------+--------+
                    |
                    +------------ Y = (AB)'
                    |
             A --| N1
                    |
             B --| N2
                    |
                   GND

(P = PMOS, ON when gate = 0; N = NMOS, ON when gate = 1.)

The two PMOS transistors are in parallel between $V_{DD}$ and the output; the two NMOS transistors are in series between the output and ground.

• A = 0 or B = 0: at least one PMOS is ON, connecting Y to $V_{DD}$, and the series NMOS path is broken → Y = 1.
• A = 1 and B = 1: both NMOS are ON, connecting Y to ground; both PMOS are OFF → Y = 0.

So $Y = \overline{AB}$. In no input state are both networks ON, so no DC current flows from $V_{DD}$ to ground.

Totem-pole output

Totem-pole output is the TTL output stage in which two transistors are stacked one above the other between $V_{CC}$ and ground, like a totem pole: Q3 (active pull-up) on top with R4 = 130 Ω and diode D1, and Q4 (pull-down) below. The output Y is taken from their junction. The phase splitter Q2 drives them in opposite phase, so only one is ON at a time.

   +5 V
    |
  R4 130
    |
    c
Q2c-b Q3   (ON for HIGH output)
    e
    |
   D1
    +------- Y
    c
Q2e-b Q4   (ON for LOW output)
    e
    |
   GND

Significance:

• Low output resistance in both states: Q3 sources current and Q4 sinks current, so load capacitance is charged and discharged quickly → short rise and fall times, higher speed than a resistor pull-up.
• Low power: no resistor carries current continuously in the LOW state, unlike a passive pull-up.
• D1 gives an extra 0.7 V drop so Q3 is surely OFF when Q4 is saturated.
• R4 limits the current spike that flows for a few ns when both transistors are briefly ON during switching.
• Limitation: totem-pole outputs must not be wired together (wired-AND); if one output is HIGH and another LOW, a large current flows and may damage the gates. Open-collector or tristate outputs are used for bus connections.

Voltage profile of TTL

The voltage profile of TTL ($V_{CC} = 5$ V) shows the voltage ranges that represent logic 0 and logic 1 at the output and at the input of a gate:

  Output (driving)       Input (receiving)
 5.0 +--------+         5.0 +--------+
     | HIGH   |             | HIGH   |
 2.4 +--------+ VOH(min) 2.0 +--------+ VIH(min)
     |invalid |  NM_H=0.4   | indet. |
 0.4 +--------+ VOL(max) 0.8 +--------+ VIL(max)
     | LOW    |  NM_L=0.4   | LOW    |
 0.0 +--------+         0.0 +--------+

• Output HIGH ≥ $V_{OH(min)} = 2.4$ V; output LOW ≤ $V_{OL(max)} = 0.4$ V.
• Input read as HIGH if ≥ $V_{IH(min)} = 2.0$ V; as LOW if ≤ $V_{IL(max)} = 0.8$ V; 0.8–2.0 V is indeterminate.
• Noise margins: $NM_H = 2.4 - 2.0 = 0.4$ V and $NM_L = 0.8 - 0.4 = 0.4$ V.

TTL to CMOS interface

When a TTL output drives a CMOS input, the LOW levels match but the HIGH levels do not:

A TTL HIGH of 2.4–3.4 V may fall in CMOS's indeterminate region. Current is not a problem, since a CMOS input draws almost no current. Methods to interface:

1. Pull-up resistor (same 5 V supply): a resistor $R_P$ (about 1–10 kΩ) is connected from the TTL output to +5 V. When the TTL output goes HIGH, Q3 of the totem pole turns off as the voltage rises and $R_P$ pulls the line up to nearly 5 V, which is a valid CMOS HIGH. When the TTL output is LOW, Q4 sinks the current $5/R_P$ (e.g. 1 mA for 4.7 kΩ), well within its 16 mA rating.

            +5 V
             |
             RP (≈ 4.7k)
             |
 TTL gate ---+----> CMOS input
   (74xx)            (74HC / 4000)

2. CMOS supply higher than 5 V (e.g. $V_{DD} = 10$–15 V): use an open-collector TTL gate (e.g. 7406/7407, rated for high voltage) with the pull-up resistor connected to $V_{DD}$, or a level-shifter IC (e.g. 4504). The output transistor switches between about 0 V and $V_{DD}$.

3. TTL-compatible CMOS: use the 74HCT/74ACT series, whose input thresholds are TTL-like ($V_{IH} = 2.0$ V, $V_{IL} = 0.8$ V), so the TTL output can be connected directly.

Input–output voltage profile of TTL

The profile shows the voltage ranges for logic 0 and 1 at the output of a driving gate and at the input of a receiving gate ($V_{CC} = 5$ V):

  Output (driving)       Input (receiving)
 5.0 +--------+         5.0 +--------+
     | HIGH   |             | HIGH   |
 2.4 +--------+ VOH(min) 2.0 +--------+ VIH(min)
     |invalid |  NM_H=0.4   | indet. |
 0.4 +--------+ VOL(max) 0.8 +--------+ VIL(max)
     | LOW    |  NM_L=0.4   | LOW    |
 0.0 +--------+         0.0 +--------+

Inputs between 0.8 V and 2.0 V are not allowed (indeterminate).

Noise margin

Noise margin is the largest noise voltage that can be added to a valid output without the next input reading a wrong level:

$$\begin{aligned} NM_H &= V_{OH(min)} - V_{IH(min)} = 2.4 - 2.0 = 0.4\ \text{V} \\ NM_L &= V_{IL(max)} - V_{OL(max)} = 0.8 - 0.4 = 0.4\ \text{V} \end{aligned}$$

So standard TTL has a noise margin of 0.4 V in both states.

Gray code

Gray code is an unweighted, unit-distance (reflected binary) code: successive numbers differ in only one bit. This avoids false intermediate codes when several bits change together, so it is used in shaft encoders, K-map ordering and error reduction. Binary to Gray: $G_{n} = B_{n}$ (MSB), $G_i = B_{i+1} \oplus B_i$.

TTL NOR gate

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Either input HIGH saturates its phase splitter (Q2A or Q2B) → Q4 ON, Q3 OFF → Y = 0. Both inputs LOW → Q2A, Q2B OFF → Q3 ON → Y = 1. So $Y = \overline{A + B}$.

Characteristics of standard TTL 74XX series

Other points: totem-pole output (fast, but outputs cannot be wired together), unconnected inputs act as HIGH (but should be tied to $V_{CC}$ through a resistor), and current spikes during switching need decoupling capacitors. Improved families (74LS, 74S, 74ALS, 74F) trade speed against power.