Flip Flops

To make a JK flip-flop from an SR flip-flop, the JK inputs and the present state $Q_n$ are fed to a small combinational circuit whose outputs drive S and R. The circuit is found from the JK characteristic table and the SR excitation table.

SR excitation table

Conversion table

K-maps

 S:        KQn=00 01 11 10       R:      KQn=00 01 11 10
   J=0        0   X  0  0          J=0      X   0  1  X
   J=1        1   X  0  1          J=1      0   0  1  0

• S: the 1s at ($J=1$, $Q_n=0$) group with the X to give $S = JQ_n'$.
• R: the 1s at ($K=1$, $Q_n=1$) give $R = KQ_n$.

$$S = J\,Q_n', \qquad R = K\,Q_n$$

Circuit

J ---[AND]----- S +---------+
Q'---[   ]        |  SR FF  |--+-- Q
                  |   CLK   |  |
K ---[AND]----- R |         |--|-+-- Q'
Q ---[   ]        +---------+  | |
  (Q and Q' fed back to the AND gates)

Check: $J = K = 1$: if $Q_n = 0$, $S = 1, R = 0$ so $Q$ sets to 1; if $Q_n = 1$, $S = 0, R = 1$ so $Q$ resets. The output toggles, and the forbidden $S = R = 1$ never occurs, because $S$ and $R$ need opposite values of $Q_n$.

A JK flip-flop is a clocked flip-flop with inputs J (like set) and K (like reset). It removes the invalid state of the SR flip-flop: when $J = K = 1$ the output toggles.

Logic diagram

It is an SR flip-flop with $Q$ and $Q'$ fed back to the input NAND gates.

J ---[NAND1]--S'-->[NAND3]---> Q
CLK -[     ]   Q'-->[     ]
Q' --[     ]
K ---[NAND2]--R'-->[NAND4]---> Q'
CLK -[     ]   Q--->[     ]
Q  --[     ]

NAND1 gets J, CLK and $Q'$; NAND2 gets K, CLK and $Q$; NAND3 and NAND4 form the cross-coupled latch.

Operation (clock active)

• $J = 0, K = 0$: both input NANDs give 1, latch holds: no change.
• $J = 0, K = 1$: if $Q = 1$, NAND2 gives 0 and resets: Q = 0.
• $J = 1, K = 0$: if $Q = 0$, NAND1 gives 0 and sets: Q = 1.
• $J = 1, K = 1$: the gate enabled by feedback changes the state: toggle.

Characteristic table

Characteristic equation

        KQn=00 01 11 10
J=0        0   1  0  0
J=1        1   1  0  1

• $J=1, Q_n=0$ (cells 100, 110) gives $JQ_n'$.
• $K=0, Q_n=1$ (cells 001, 101) gives $K'Q_n$.

$$Q_{n+1} = J\,Q_n' + K'\,Q_n$$

Excitation table

Shows the inputs needed for each required transition:

For example, for $0 \to 1$ we may use $J=1, K=0$ (set) or $J=1, K=1$ (toggle), so $K$ is a don't care.

Note: with a level-triggered JK and $J = K = 1$, the output can toggle many times while the clock is high (race-around condition). It is removed by using an edge-triggered or master-slave JK flip-flop.

An edge-triggered S-R flip-flop changes state only at the active edge of the clock (rising edge for positive-edge, falling edge for negative-edge). At all other times, changes on S and R have no effect. It is made of a clocked SR latch with a pulse-transition (edge) detector on the clock input.

Circuit

           +-------------+
S -------->| NAND  NAND  |--+-- Q
           | steering    |  |
CLK-[edge]>| gates latch |  |
  detector | NAND  NAND  |--+-- Q'
R -------->|             |
           +-------------+

Edge detector (positive edge):
CLK --+----------[AND]--> narrow pulse
      +-[NOT]----[   ]
       (delay of NOT gives a short spike)

The NOT gate's delay makes $CLK$ and $\overline{CLK}$ both 1 for a few nanoseconds just after the rising edge, so the AND gives a very narrow pulse. Only during this pulse are the steering gates enabled and the latch can change.

Truth table (positive-edge-triggered)

Timing diagram

edge   1     2     3     4     5
CLK  __|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__
S    ‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾
R    _____|‾‾‾‾‾‾‾‾‾‾‾|______________
Q    __|‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾

• Edge 1: $S=1, R=0$: Q sets to 1.
• Edge 2: $S=0, R=1$: Q resets to 0.
• Edge 3: $S=0, R=1$: Q stays 0.
• Edge 4: $S=1, R=0$: Q sets to 1.
• Edge 5: $S=1, R=0$: Q stays 1.

Q changes only just after a rising edge, even though S and R change at other times. This sampling at one instant makes edge-triggered flip-flops suitable for synchronous counters and registers. A negative-edge-triggered SR flip-flop works the same way, but on the falling edge (shown by a bubble with the triangle at CLK).

Triggering is the way a clock signal makes a flip-flop or latch change state. In level triggering the output responds to the inputs during the whole time the clock is at its active level (HIGH or LOW). In edge triggering the output responds only at the instant of a clock transition (rising or falling edge).

CLK      ___|‾‾‾‾‾‾‾|___
Level:      [ active ]     (whole HIGH time)
+ve edge:   ^              (only at rise)
-ve edge:           v      (only at fall)

Example: in a D latch with $EN = 1$, Q follows D continuously ("transparent"). In a positive-edge D flip-flop, Q takes the value of D only at the rising edge and holds it until the next rising edge.

Negative edge-triggered JK flip-flop

A negative edge-triggered JK flip-flop changes state only at the falling (HIGH-to-LOW) edge of the clock. An edge detector produces a narrow pulse at the falling edge, and only during that pulse are J and K allowed to act. Its symbol has a triangle with a bubble at CLK. Since the inputs act for a very short time, the output can change only once per clock, so there is no race-around.

Converting T flip-flop into JK flip-flop

We need a circuit with inputs J, K, $Q_n$ whose output drives T. T excitation: $T = 1$ when the state must change.

K-map for T

        KQn=00 01 11 10
J=0        0   0  1  0
J=1        1   0  1  1

• Cells 011, 111 ($K=1$, $Q_n=1$) give $KQ_n$.
• Cells 100, 110 ($J=1$, $Q_n=0$) give $JQ_n'$.

$$T = J\,Q_n' + K\,Q_n$$

Circuit

J --[AND]--+
Q'--[   ]  +--[OR]-- T +--------+--- Q
K --[AND]--+           | T FF   |
Q --[   ]              |  CLK   |--- Q'
                       +--------+
 (Q and Q' fed back to the AND gates)

Check: $J = K = 1$ gives $T = Q_n' + Q_n = 1$, so it toggles; $J = K = 0$ gives $T = 0$, no change.

Logic diagram (clocked SR flip-flop, NAND)

S ---[NAND1]--S'-->[NAND3]---> Q
CLK -[     ]   Q'-->[     ]
CLK -[NAND2]--R'-->[NAND4]---> Q'
R ---[     ]   Q--->[     ]
 (Q fed to NAND4, Q' fed to NAND3)

NAND1 and NAND2 are steering gates enabled by CLK; NAND3 and NAND4 are cross-coupled (each output feeds the other's input). When CLK = 1: $S = 1$ sets Q to 1, $R = 1$ resets Q to 0, $S = R = 0$ holds, and $S = R = 1$ is not allowed.

Excitation table

Characteristic equation

From the characteristic table ($S = R = 1$ taken as don't care):

        RQn=00 01 11 10
S=0        0   1  0  0
S=1        1   1  X  X

• The $S = 1$ row (with X) gives $S$; cells 001, 101 give $R'Q_n$.

$$Q_{n+1} = S + R'\,Q_n, \qquad \text{with } SR = 0$$

Setup time and hold time

• Setup time ($t_{su}$): the minimum time the data input (D, J, K, S, R) must be stable before the active clock edge so that the flip-flop reads it correctly.
• Hold time ($t_h$): the minimum time the data input must stay stable after the active clock edge.

Data   ===X======STABLE=======X====
             |<-tsu->|<-th->|
CLK    ______________|‾‾‾‾‾‾‾‾‾‾‾‾
                     ^ active edge

If either is violated the flip-flop may store a wrong value or go metastable. Both are given in the data sheet; for LS-TTL flip-flops they are of the order of tens of ns ($t_{su}$) and a few ns ($t_h$).

SR flip-flop into JK flip-flop

We add a combinational circuit with inputs J, K and $Q_n$ that drives S and R.

SR excitation table

Conversion table

K-maps

 S:      KQn=00 01 11 10    R:     KQn=00 01 11 10
  J=0       0   X  0  0      J=0      X   0  1  X
  J=1       1   X  0  1      J=1      0   0  1  0

$$S = J\,Q_n', \qquad R = K\,Q_n$$

Circuit

J --[AND]-- S +--------+--+-- Q
Q'--[   ]     | SR FF  |  |
              |  CLK   |  |
K --[AND]-- R |        |--|-+-- Q'
Q --[   ]     +--------+  | |
   (feedback of Q, Q' to the AND gates)

Check: $J = K = 1$, $Q_n = 1$: $S = 0$, $R = 1$, so Q resets (toggle). The two AND gates never make $S = R = 1$, so the invalid state is removed.

D flip-flop into JK flip-flop

Find D (the input of the available flip-flop) for each J, K, $Q_n$. D excitation: $D = Q_{n+1}$.

        KQn=00 01 11 10
J=0        0   1  0  0
J=1        1   1  0  1

$$D = J\,Q_n' + K'\,Q_n$$

J --[AND]--+
Q'--[   ]  +--[OR]-- D +--------+--- Q
K'--[AND]--+           | D FF   |
Q --[   ]              |  CLK   |--- Q'
                       +--------+

JK flip-flop into D flip-flop

Find J, K for each D, $Q_n$, using the JK excitation table.

From the table (using don't cares): $J = D$, $K = D'$.

D --+------------ J +--------+--- Q
    |               | JK FF  |
    +--[NOT]----- K |  CLK   |--- Q'
                    +--------+

So D goes to J directly and through an inverter to K. Then $D = 1$ sets and $D = 0$ resets the flip-flop at each clock, which is D flip-flop behaviour.

Eliminating switch contact bounce

When a mechanical switch is closed or opened, its contacts bounce several times for a few milliseconds, so a digital circuit sees many pulses instead of one clean transition.

Method 1: SR (NAND) latch debouncer using an SPDT switch:

 +5V-[R1]-+-------S'-->+--------+
          |            | NAND   |--> Q (clean)
     A  o-+            | SR     |
         \             | latch  |--> Q'
  GND --o  (arm)       |        |
     B  o-+            |        |
          |            |        |
 +5V-[R2]-+-------R'-->+--------+

• When the switch moves from A to B, the first touch at B resets the latch.
• Bounces at B only make R' go 1, 0, 1, ... ; with S' = 1 and R' = 1 the latch holds its state, so the output stays clean.
• The output changes only once, at the first contact.

Method 2: an RC filter followed by a Schmitt-trigger inverter (e.g. 74HC14); the capacitor smooths the bounces and the hysteresis gives one clean edge. Method 3: software delay (about 10–20 ms) in microcontrollers.

Negative edge-triggered RS flip-flop

It changes state only at the falling edge of the clock. An edge detector makes a very narrow pulse when CLK goes from 1 to 0; only during this pulse are the steering gates enabled. Symbol: triangle with a bubble at CLK.

S ----[NAND]--+   +--------+
CLK-[edge  ]  +-->| cross- |--- Q
    [detect]--+-->| coupled|
R ----[NAND]--+   | latch  |--- Q'
                  +--------+

Excitation table

Characteristic equation: $Q_{n+1} = S + R'Q_n$ with $SR = 0$.

Positive edge-triggered S-R flip-flop

It changes state only at the rising (LOW-to-HIGH) edge of the clock. A pulse-transition detector (CLK ANDed with its delayed inverse) gives a very narrow pulse at each rising edge, which enables the NAND steering gates of an SR latch for a moment. S and R values at other times are ignored. Symbol: triangle at CLK (no bubble).

Excitation table

Characteristic equation

        RQn=00 01 11 10
S=0        0   1  0  0
S=1        1   1  X  X

$S = R = 1$ is a don't care. Grouping gives $S$ (bottom row) and $R'Q_n$ (cells 001, 101):

$$Q_{n+1} = S + R'\,Q_n, \qquad SR = 0$$

State diagram

Two states, Q = 0 and Q = 1; arcs labelled with SR.

   SR=00,01              SR=00,10
    +---+    SR=10        +---+
    |   v  ---------->    |   v
   ( Q=0 )              ( Q=1 )
           <----------
              SR=01

• In state 0: $SR = 00$ or $01$ keeps $Q = 0$; $SR = 10$ moves to state 1.
• In state 1: $SR = 00$ or $10$ keeps $Q = 1$; $SR = 01$ moves to state 0.
• $SR = 11$ is not allowed.

An edge-triggered J-K flip-flop changes its output only at the active edge (here the rising edge) of the clock. At that instant J and K decide whether Q is held, reset, set or toggled; at all other times the inputs have no effect.

Circuit

The flip-flop is a clocked J-K circuit (two input NAND gates plus a NAND latch) driven by a narrow pulse CLK* produced by an edge detector.

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

Operation

CLK* is high only for a very short time $\Delta t$ (a few ns) after each rising edge, so gates G1 and G2 are enabled only at that instant. Because the pulse is shorter than the propagation delay of the latch, the output changes at most once per edge (no race-around).

1. J = 0, K = 0: G1 and G2 outputs stay 1, the latch keeps its state: $Q_{n+1} = Q_n$.
2. J = 0, K = 1: if Q = 1, G2 (inputs K, CLK*, Q all 1) gives 0 and resets the latch: Q = 0. If Q is already 0, nothing changes.
3. J = 1, K = 0: if Q = 0, then Q' = 1 and G1 gives 0, which sets the latch: Q = 1.
4. J = 1, K = 1: the gate fed by the "active" output fires: if Q = 0, G1 sets it; if Q = 1, G2 resets it. The output toggles.

Truth (characteristic) table

Characteristic equation:

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Excitation table

The excitation table gives the inputs needed for a required transition $Q_n \to Q_{n+1}$ (x = don't care). It is used when designing counters and sequential circuits.

• 0 to 0: J must be 0 (hold or reset both keep 0), so K = x.
• 0 to 1: J must be 1 (set or toggle), K = x.
• 1 to 0: K must be 1 (reset or toggle), J = x.
• 1 to 1: K must be 0 (hold or set), J = x.

Timing diagram (positive edge, Q starts at 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__

Combinational vs sequential circuit

Latch as a switch bounce eliminator

Contact bounce: when a mechanical switch is thrown, the metal contact hits the new terminal and bounces several times for a few milliseconds before it settles. A logic input connected directly to the switch therefore sees a burst of 0-1-0-1 pulses instead of one clean change. A counter would count every bounce.

A NAND S'-R' latch with a single-pole double-throw (SPDT) switch removes these pulses:

        +5V                    +5V
         |                      |
        [R1]                   [R2]
         |                      |
  S' <---+---o A          B o---+---> R'
              \          /
               \___o____/  switch arm
                   |       (touches A or B)
                  GND
          +---------------+
 S' ----->| NAND S'-R'    |---> Q
 R' ----->| latch         |---> Q'
          +---------------+

How it works

1. With the switch at position A, S' = 0 and R' = 1 (pulled up by R2). The latch is set: Q = 1.
2. When the switch is moved towards B, it first leaves A. Now S' = R' = 1 (both pulled up): the latch is in the hold state and Q stays 1.
3. The first time the contact touches B, R' = 0 and the latch resets: Q = 0.
4. The contact now bounces: it leaves B (R' = 1, hold, Q stays 0) and touches B again (reset again, Q stays 0). The bounce never reaches A, so S' never becomes 0.
5. Hence Q makes a single clean transition from 1 to 0 at the first contact. Moving the switch back to A gives a single clean 0-to-1 transition in the same way.

 R' (at B)  ‾‾‾‾‾|_|‾|_|‾|________
 Q          ‾‾‾‾‾|________________
              first touch: one clean edge

The latch works because its "hold" condition (S' = R' = 1) ignores the open-contact gaps during bouncing, while the first contact already set the final state.

Drawback of S-R flip-flop

• With S = R = 1 (both active) both outputs are forced to the same level, so Q and Q' are no longer complements. This input is forbidden/invalid.
• When S and R return from 1,1 to 0,0 together, the next state depends on which gate is faster, so the output is unpredictable (race).
• The designer must always make sure S and R are never both 1, which limits its use. (The J-K flip-flop removes this drawback by toggling for J = K = 1.)

Edge-triggered J-K flip-flop

An edge-triggered J-K flip-flop responds to J and K only at the active (here rising) clock edge. A small edge-detector circuit turns each rising edge into a very narrow pulse CLK* that enables the input gates.

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

Operation

• J = K = 0: G1 and G2 are disabled (output 1), the latch holds: no change.
• J = 0, K = 1: at the edge G2 gives 0 only if Q = 1, so the flip-flop resets (Q = 0).
• J = 1, K = 0: at the edge G1 gives 0 only if Q' = 1, so the flip-flop sets (Q = 1).
• J = K = 1: the gate whose feedback input is 1 fires, so the output toggles. Since CLK* is narrower than the propagation delay, it toggles only once per edge (no race-around).

Truth table

Timing diagram (output changes only at rising edges; Q starts at 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__

Setup time and hold time

• Setup time ($t_s$ or $t_{su}$): the minimum time for which the data input(s) (D, J-K, S-R) must be stable before the active clock edge, so that the flip-flop reads them correctly.
• Hold time ($t_h$): the minimum time for which the data input(s) must remain stable after the active clock edge.

 CLK   ________|‾‾‾‾‾‾‾‾
 D     XXXX|‾‾‾‾‾‾‾‾|XXX
           |<-ts->|<th>|
                  ^ active edge

If either is violated, the output may be wrong or may go into a metastable state. Typical TTL values: $t_s \approx 20$ ns, $t_h \approx 5$ ns.

Method of conversion

1. Write the characteristic table of the required flip-flop (inputs and $Q_n$ give $Q_{n+1}$).
2. For each row, read the inputs needed on the available (S-R) flip-flop from its excitation table.
3. Simplify the S and R expressions with K-maps and build the input logic.

S-R excitation table used:

R-S to D flip-flop

K-map for S
Q\D    0   1
 0     0   1
 1     0   x

K-map for R
Q\D    0   1
 0     x   0
 1     1   0

$$S = D, \qquad R = \overline{D}$$

              +---------+
 D --+------->| S     Q |---> Q
     |   CLK->|>  SR    |
     +-[NOT]->| R    Q' |---> Q'
              +---------+

Since R is always the complement of S, the forbidden input S = R = 1 can never occur.

R-S to J-K flip-flop

K-map for S
Q\JK   00  01  11  10
 0      0   0   1   1
 1      x   0   0   x

K-map for R
Q\JK   00  01  11  10
 0      x   x   0   0
 1      0   1   1   0

$$S = J\,\overline{Q}, \qquad R = K\,Q$$

            +-----+      +---------+
 J -------->|     |      |         |
 Q' ------->| AND |----->| S     Q |---> Q
            +-----+      |         |
            +-----+ CLK->|>  SR    |
 K -------->|     |      |         |
 Q  ------->| AND |----->| R    Q' |---> Q'
            +-----+      +---------+
 (Q and Q' are fed back from the outputs)

Check: for J = K = 1 with Q = 0, S = 1, R = 0 (set); with Q = 1, S = 0, R = 1 (reset), so the output toggles and S = R = 1 never occurs.

Characteristic equation of J-K flip-flop

The characteristic table lists the next state $Q_{n+1}$ for every combination of J, K and present state $Q_n$:

(J K = 00 hold, 01 reset, 10 set, 11 toggle.)

Plotting $Q_{n+1}$ on a 3-variable K-map:

K-map for Q+ (rows Q, columns JK)
Q\JK   00  01  11  10
 0      0   0   1   1
 1      1   0   0   1
 Groups: J.Q' (row 0, cells 11,10)
         K'.Q (row 1, cells 00,10)

• Row Q = 0, columns JK = 11 and 10 give $J\,\overline{Q_n}$.
• Row Q = 1, columns JK = 00 and 10 give $\overline{K}\,Q_n$.

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Making a toggle (T) flip-flop

Connect J and K together and call the common input T (or tie J = K = 1 for permanent toggling).

          +---------+
 T --+----| J     Q |--- Q
     |    |         |
     | CLK|>  JK    |
     |    |         |
     +----| K    Q' |--- Q'
          +---------+

With J = K = T, the equation becomes

$$Q_{n+1} = T\,\overline{Q_n} + \overline{T}\,Q_n = T \oplus Q_n$$

so T = 0 holds the state and T = 1 toggles it at every clock edge (a divide-by-2 circuit when T = 1).

Input and output waveforms (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__

A positive edge-triggered J-K flip-flop samples J and K only at the rising (0 to 1) edge of the clock. It is built from a clocked J-K NAND circuit whose clock input is a narrow pulse produced by an edge detector.

Circuit diagram

Edge detector (pulse-transition detector):

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK

The NOT gate delays and inverts CLK. Just after CLK rises, the inverter output is still 1 for its propagation delay $\Delta t$, so the AND gate gives a narrow spike CLK*. After the rising edge, at the falling edge and at all other times, CLK* = 0.

J-K section (NAND gates):

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

      +---------+
 J ---| J     Q |--- Q
 CLK -|>        |
 K ---| K    Q' |--- Q'
      +---------+
 '>' = edge triggered (a bubble 'o>' means
 negative edge triggered)

Operation

G1 has inputs J, CLK*, Q'; G2 has inputs K, CLK*, Q. G3-G4 form an active-low S'-R' latch.

1. No rising edge (CLK = 0):* G1 = G2 = 1, latch holds: Q unchanged whatever J, K are.
2. J = 0, K = 0: G1 = G2 = 1 even at the edge: no change.
3. J = 0, K = 1: at the edge, G2 = (K·CLK*·Q)' = 0 if Q = 1, so the latch resets (Q = 0). If Q was 0 it stays 0.
4. J = 1, K = 0: at the edge, G1 = (J·CLK*·Q')' = 0 if Q = 0, so the latch sets (Q = 1). If Q was 1 it stays 1.
5. J = 1, K = 1: if Q = 0, G1 fires and sets; if Q = 1, G2 fires and resets. Output toggles. Since CLK* lasts less than the propagation delay of the latch, the new output arrives after CLK* is over, so only one toggle happens per edge.

Truth table

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Timing diagram (Q initially 0, changes only at rising edges)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__

Drawbacks of J-K flip-flop

• In a level-triggered J-K flip-flop with J = K = 1, the output toggles many times while the clock is high (race-around condition); edge triggering or master-slave construction is needed to avoid it.
• Edge triggering depends on a very narrow pulse whose width (gate delay) is hard to control; it needs two inputs and more gates than a D flip-flop, so it is not convenient for simple data storage.

Drawbacks of S-R flip-flop

• With S = R = 1 (both active) both outputs are forced to the same level, so Q and Q' are no longer complements. This input is forbidden/invalid.
• When S and R return from 1,1 to 0,0 together, the next state depends on which gate is faster, so the output is unpredictable (race).
• The designer must always make sure S and R are never both 1, which limits its use. (The J-K flip-flop removes this drawback by toggling for J = K = 1.)

Data (D) flip-flop

A D (data or delay) flip-flop has a single data input D. At the active clock edge, the value of D is copied to Q and held until the next active edge: $Q_{n+1} = D$. It is built from a clocked S-R flip-flop by connecting D to S and D' to R through an inverter, which removes the invalid state.

Logic diagram

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

Graphic symbol

      +---------+
 D ---| D     Q |--- Q
 CLK -|>        |
      |      Q' |--- Q'
      +---------+

Operation

1. Clock inactive (no edge / CLK = 0): G1 and G2 outputs are 1, the NAND latch holds the previous state.
2. D = 1 at the clock: S = 1, R = 0. G1 output S* = 0 sets the latch: Q = 1.
3. D = 0 at the clock: S = 0, R = 1. G2 output R* = 0 resets the latch: Q = 0.
4. S and R are always complements, so the forbidden S = R = 1 state never appears.

Because the output follows the input with a delay of one clock, it is also called a delay flip-flop; it is the basic element of registers and memory.

Truth table

Characteristic equation: $Q_{n+1} = D$.

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
D     ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾

At every rising edge Q takes the value D had just before that edge (D sequence 1, 1, 0, 1, 0, 0, 1 gives Q = 1, 1, 0, 1, 0, 0, 1); changes of D between edges are ignored.

An edge-triggered J-K flip-flop changes state only at one edge of the clock (rising edge for positive edge triggering). It consists of an edge (pulse-transition) detector and a J-K NAND circuit.

Circuit diagram

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

Explanation

• Edge detector: the inverter delays CLK by its propagation delay $\Delta t$. For this short time after a rising edge both AND inputs are 1, so CLK* is a narrow positive spike. This spike enables G1 and G2 only at the edge.
• Input gates: G1 receives J, CLK*, Q'; G2 receives K, CLK*, Q. Their outputs drive the active-low inputs of the G3-G4 latch.

Characteristic equation: $Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$.

The CLK* pulse ends before the change of Q can travel back to G1/G2, so for J = K = 1 the output toggles only once per clock edge. This removes the race-around problem of the level-triggered J-K flip-flop.

Synchronous vs asynchronous sequential circuits

Converting S-R flip-flop into J-K flip-flop

Step 1: excitation table of the available S-R flip-flop

Step 2: conversion table. For each J, K and present state Q, find Q+ from the J-K characteristic table, then write the S and R needed for that change:

Step 3: K-maps

K-map for S
Q\JK   00  01  11  10
 0      0   0   1   1
 1      x   0   0   x

K-map for R
Q\JK   00  01  11  10
 0      x   x   0   0
 1      0   1   1   0

• S: the 1s are at Q = 0, JK = 11 and 10; the don't-cares at Q = 1 cannot enlarge this group (Q = 1, JK = 11 is 0), so $S = J\overline{Q}$.
• R: the 1s are at Q = 1, JK = 01 and 11, so $R = KQ$.

$$S = J\,\overline{Q}, \qquad R = K\,Q$$

Step 4: circuit

            +-----+      +---------+
 J -------->|     |      |         |
 Q' ------->| AND |----->| S     Q |---> Q
            +-----+      |         |
            +-----+ CLK->|>  SR    |
 K -------->|     |      |         |
 Q  ------->| AND |----->| R    Q' |---> Q'
            +-----+      +---------+
 (Q and Q' are fed back from the outputs)

Check: J = K = 1 with Q = 0 gives S = 1, R = 0 (Q becomes 1); with Q = 1 gives S = 0, R = 1 (Q becomes 0). So the circuit toggles, and S = R = 1 can never occur because S needs Q = 0 while R needs Q = 1.

A J-K flip-flop is an improved S-R flip-flop: J acts like Set, K like Reset, and the input J = K = 1, which is invalid for S-R, makes the output toggle.

Logic diagram (clocked J-K using NAND gates)

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK -----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK -----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3-G4: cross-coupled NAND latch. Q' is fed
 back to G1 and Q to G2.

G1 gets J, CLK and Q'; G2 gets K, CLK and Q; G3-G4 form a NAND latch. In practice the clock is an edge (or master-slave) clock so that the output changes once per clock.

Graphic symbol

      +---------+
 J ---| J     Q |--- Q
 CLK -|>        |
 K ---| K    Q' |--- Q'
      +---------+
 '>' = edge triggered (a bubble 'o>' means
 negative edge triggered)

Operation

• J = 0, K = 0: G1 = G2 = 1, latch holds: no change.
• J = 0, K = 1: G2 = 0 when Q = 1, latch resets: Q = 0.
• J = 1, K = 0: G1 = 0 when Q = 0, latch sets: Q = 1.
• J = 1, K = 1: only the gate with the 1 feedback fires, so the output toggles: Q+ = Q'.
• No clock: inputs ignored, output held.

Characteristic table

Characteristic equation

K-map for Q+ (rows Q, columns JK)
Q\JK   00  01  11  10
 0      0   0   1   1
 1      1   0   0   1
 Groups: J.Q' (row 0, cells 11,10)
         K'.Q (row 1, cells 00,10)

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

State diagram

The flip-flop has two states, Q = 0 and Q = 1. Each arrow is labelled with the J K inputs that cause that transition at the clock edge (x = don't care):

              JK = 1x
     +-------------------------+
     |                         v
  +-------+               +-------+
  | Q = 0 |               | Q = 1 |
  +-------+               +-------+
     ^                         |
     +-------------------------+
              JK = x1
 Self-loop on Q=0: JK = 0x (00 or 01)
 Self-loop on Q=1: JK = x0 (00 or 10)

• From 0: stays 0 for JK = 00 (hold) or 01 (reset); goes to 1 for 10 (set) or 11 (toggle).
• From 1: stays 1 for JK = 00 or 10; goes to 0 for 01 or 11.

These labels are exactly the excitation table: 0 to 1 needs J = 1, K = x; 1 to 0 needs J = x, K = 1.

Advantages of J-K over S-R flip-flop

• No invalid state: for S = R = 1 the S-R output is undefined, but J = K = 1 makes the J-K flip-flop toggle, a useful defined state.
• Because it can toggle, it can work as a T flip-flop and is the basic element of counters and frequency dividers.
• It is a universal flip-flop: S-R, D and T operations can all be obtained from it.
• Its excitation table has many don't-cares, which gives simpler logic in counter design.

D flip-flop

A D flip-flop has one data input. At each active clock edge, the output Q becomes equal to D and stays so until the next active edge: $Q_{n+1} = D$. It is made from an S-R flip-flop with an inverter between S and R, so S = R = 1 never occurs.

Logic diagram

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

Symbol

      +---------+
 D ---| D     Q |--- Q
 CLK -|>        |
      |      Q' |--- Q'
      +---------+

Operation

• CLK inactive: G1 = G2 = 1, the latch keeps its previous state.
• D = 1 at the clock: S = 1, R = 0, G1 output goes 0 and sets the latch, Q = 1.
• D = 0 at the clock: S = 0, R = 1, G2 output goes 0 and resets the latch, Q = 0.

Truth table

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
D     ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾

Q copies D at each rising edge only, so the output is the input delayed by one clock period. D flip-flops are used in registers, latches for data and as delay elements.

To make a T flip-flop behave as a J-K flip-flop, we add input logic that produces T from J, K and the present state Q. The required J-K behaviour: JK = 00 hold, 01 reset, 10 set, 11 toggle.

Step 1: excitation table of T flip-flop (T = 1 whenever the state must change)

Step 2: conversion table. For each J, K and Q, take Q+ from the J-K characteristic table and write the T needed:

Step 3: K-map for T

K-map for T
Q\JK   00  01  11  10
 0      0   0   1   1
 1      0   1   1   0

• Group Q = 0, JK = 11 and 10: $J\overline{Q}$.
• Group Q = 1, JK = 01 and 11: $KQ$.

$$T = J\,\overline{Q} + K\,Q$$

Step 4: logic circuit

          +-----+
 J ------>|     |
 Q' ----->| AND |--+
          +-----+  |  +----+     +---------+
                   +->|    |     |         |
                      | OR |---->| T     Q |---> Q
                   +->|    |CLK->|>   T    |
          +-----+  |  +----+     |      Q' |---> Q'
 K ------>|     |  |             +---------+
 Q  ----->| AND |--+
          +-----+
 (Q and Q' are fed back from the outputs)

Check: J = K = 1 gives $T = \overline{Q} + Q = 1$ (toggle); J = K = 0 gives T = 0 (hold); J = 1, K = 0 gives $T = \overline{Q}$, so a 0 toggles to 1 and a 1 holds (set); J = 0, K = 1 gives T = Q (reset).

D flip-flop

The output copies the D input at each active clock edge: $Q_{n+1} = D$.

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

T flip-flop

The T (toggle) flip-flop holds its state for T = 0 and complements it for T = 1: $Q_{n+1} = T \oplus Q_n$. It is made from a J-K flip-flop with J and K tied together.

          +---------+
 T --+----| J     Q |--- Q
     |    |         |
     | CLK|>  JK    |
     |    |         |
     +----| K    Q' |--- Q'
          +---------+

T flip-flops are used in counters and as divide-by-2 circuits (T = 1).

Converting T flip-flop into J-K flip-flop

Step 1: excitation table of T flip-flop (T = 1 whenever the state must change)

Step 2: conversion table. For each J, K and Q, take Q+ from the J-K characteristic table and write the T needed:

Step 3: K-map for T

K-map for T
Q\JK   00  01  11  10
 0      0   0   1   1
 1      0   1   1   0

• Group Q = 0, JK = 11 and 10: $J\overline{Q}$.
• Group Q = 1, JK = 01 and 11: $KQ$.

$$T = J\,\overline{Q} + K\,Q$$

Step 4: logic circuit

          +-----+
 J ------>|     |
 Q' ----->| AND |--+
          +-----+  |  +----+     +---------+
                   +->|    |     |         |
                      | OR |---->| T     Q |---> Q
                   +->|    |CLK->|>   T    |
          +-----+  |  +----+     |      Q' |---> Q'
 K ------>|     |  |             +---------+
 Q  ----->| AND |--+
          +-----+
 (Q and Q' are fed back from the outputs)

Check: J = K = 1 gives $T = \overline{Q} + Q = 1$ (toggle); J = K = 0 gives T = 0 (hold); J = 1, K = 0 gives $T = \overline{Q}$, so a 0 toggles to 1 and a 1 holds (set); J = 0, K = 1 gives T = Q (reset).

Flip-flop as a state machine

A state machine is a circuit whose output depends on its present state and inputs, and which moves from one state to the next at each clock. A flip-flop is the simplest state machine:

• It stores one bit, so it has two states, Q = 0 and Q = 1. The stored value is the present state.
• At each clock edge, the next state is decided by the inputs and the present state through its characteristic equation (e.g. $Q_{n+1} = J\overline{Q} + \overline{K}Q$).
• Its behaviour can be drawn as a state diagram with two circles and arrows labelled with inputs, exactly like any finite state machine:

              JK = 1x
     +-------------------------+
     |                         v
  +-------+               +-------+
  | Q = 0 |               | Q = 1 |
  +-------+               +-------+
     ^                         |
     +-------------------------+
              JK = x1
 Self-loop on Q=0: JK = 0x (00 or 01)
 Self-loop on Q=1: JK = x0 (00 or 10)

• With n flip-flops plus next-state logic, a machine with up to $2^n$ states (counter, sequence detector) is built.

Converting S-R flip-flop to J-K flip-flop

S-R excitation table:

Conversion table (Q+ from the J-K table, then S, R from the S-R excitation table):

K-maps:

K-map for S
Q\JK   00  01  11  10
 0      0   0   1   1
 1      x   0   0   x

K-map for R
Q\JK   00  01  11  10
 0      x   x   0   0
 1      0   1   1   0

$$S = J\,\overline{Q}, \qquad R = K\,Q$$

            +-----+      +---------+
 J -------->|     |      |         |
 Q' ------->| AND |----->| S     Q |---> Q
            +-----+      |         |
            +-----+ CLK->|>  SR    |
 K -------->|     |      |         |
 Q  ------->| AND |----->| R    Q' |---> Q'
            +-----+      +---------+
 (Q and Q' are fed back from the outputs)

For J = K = 1, S = Q' and R = Q, so the circuit toggles and the forbidden S = R = 1 never occurs.

A D (data/delay) flip-flop has a single input D. At the active clock edge, Q takes the value of D and holds it until the next active edge. It is formed from a clocked S-R flip-flop by feeding D to S and D' to R.

Logic diagram

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

Symbol

      +---------+
 D ---| D     Q |--- Q
 CLK -|>        |
      |      Q' |--- Q'
      +---------+

Operation

1. No active clock: G1 and G2 outputs are 1, so the NAND latch (G3, G4) keeps the old state.
2. D = 1 at the clock: S = 1, R = 0. G1 gives S* = 0, which sets the latch: Q = 1, Q' = 0.
3. D = 0 at the clock: S = 0, R = 1. G2 gives R* = 0, which resets the latch: Q = 0, Q' = 1.
4. The inverter guarantees $S \neq R$, so the invalid S = R = 1 condition of the S-R flip-flop is removed.

Truth (characteristic) table

Characteristic equation: $Q_{n+1} = D$.

Excitation table

To produce a required change $Q \to Q_{n+1}$, D must simply equal the next state:

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
D     ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾

Q follows D only at rising edges, so Q is D delayed by up to one clock period.

Converting S-R flip-flop to T flip-flop

A T flip-flop must hold for T = 0 and toggle for T = 1. We generate S and R from T and Q.

S-R excitation table:

Conversion table (Q+ = T XOR Q, then S and R from the excitation table):

K-maps:

K-map for S
Q\T    0   1
 0     0   1
 1     x   0

K-map for R
Q\T    0   1
 0     x   0
 1     0   1

$$S = T\,\overline{Q}, \qquad R = T\,Q$$

            +-----+      +---------+
 T --+----->|     |      |         |
     | Q' ->| AND |----->| S     Q |---> Q
     |      +-----+      |         |
     |      +-----+ CLK->|>  SR    |
     +----->|     |      |         |
       Q -->| AND |----->| R    Q' |---> Q'
            +-----+      +---------+
 (Q and Q' are fed back from the outputs)

Check: T = 1, Q = 0 gives S = 1, R = 0 (Q goes to 1); T = 1, Q = 1 gives S = 0, R = 1 (Q goes to 0); T = 0 gives S = R = 0 (hold). S and R are never 1 together.

Timing diagram of S-R flip-flop (positive edge triggered, Q initially 0)

       1   2   3   4   5   6
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
S     ‾‾‾|___________|‾‾‾|____
R     _______|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|_______|‾‾‾|__

S = 1 sets Q at an edge, R = 1 resets it, S = R = 0 keeps the old value. S = R = 1 is not applied because it is invalid.

Race-around condition

In a level-triggered J-K flip-flop with J = K = 1, the output toggles once after one propagation delay $\Delta t$. If the clock is still high, the new output feeds back to the input gates and makes it toggle again, and again, as long as CLK = 1. At the end of the pulse the output state is unpredictable. This repeated toggling during one clock pulse is the race-around condition. It happens when the clock pulse width $t_p > \Delta t$.

 CLK  ___|‾‾‾‾‾‾‾‾‾‾‾‾|___
 Q    ___|‾‾|__|‾‾|__|‾‾‾   (J = K = 1)

It is avoided by keeping $t_p < \Delta t < T$, by edge triggering, or by a master-slave J-K flip-flop.

Limitations of S-R flip-flop

• S = R = 1 is a forbidden input: both outputs become equal (not complements).
• If S and R go from 1,1 to 0,0 together, the final state is indeterminate (depends on gate speeds).
• So the circuit using it must always prevent S = R = 1; it cannot toggle and is not directly useful for counters.

Converting J-K flip-flop to S-R flip-flop

J-K excitation table:

Conversion table (Q+ from the S-R table; S = R = 1 is not allowed, so those rows are don't-cares):

K-maps:

K-map for J
Q\SR   00  01  11  10
 0      0   0   x   1
 1      x   x   x   x

K-map for K
Q\SR   00  01  11  10
 0      x   x   x   x
 1      0   1   x   0

$$J = S, \qquad K = R$$

          +---------+
 S -------| J     Q |--- Q
 CLK -----|>  JK    |
 R -------| K    Q' |--- Q'
          +---------+

A J-K flip-flop works as an S-R flip-flop with S connected to J and R connected to K directly; no extra gates are needed. (For S = R = 1 it toggles instead of giving an invalid output, but that input is still not used for S-R operation.)

Combinational vs sequential circuit

Master-slave J-K flip-flop

A master-slave J-K flip-flop is two clocked latches in series: the master is enabled by CLK and the slave by the inverted clock CLK'. The final outputs Q and Q' are fed back to the master's input gates. It was designed to remove the race-around condition of the level-triggered J-K flip-flop.

        +---------+   Qm   +---------+
 J -----| MASTER  |------->|  SLAVE  |----> Q
        | SR latch|        | SR latch|
 K -----| (gated) |------->| (gated) |----> Q'
        +---------+   Qm'  +---------+
             ^                  ^
 CLK --------+-----[NOT]--------+
 Master enabled when CLK=1, slave when CLK=0.
 Q' is fed back to the J gate and Q to the
 K gate of the master.

Working principle

1. CLK = 1 (master active, slave disabled): the master reads J, K and the fed-back Q, Q' and sets its outputs Qm, Qm' (J = 1, K = 0 sets Qm; J = 0, K = 1 resets Qm; J = K = 1 makes Qm the complement of Q; J = K = 0 holds). The slave is closed, so Q does not change.
2. CLK goes 1 to 0: the master is disabled and freezes Qm. The slave becomes enabled.
3. CLK = 0 (slave active): the slave copies the master (Q = Qm). Since the master is closed, changing Q cannot affect the master during this time.
4. So the output changes only once per clock pulse, at the falling edge, and Q never feeds back into an active master. Toggling for J = K = 1 happens only once, which removes race-around.

 CLK  __|‾‾‾‾|____|‾‾‾‾|____
 Qm   __|‾‾‾‾‾‾‾‾‾|________   (J = K = 1)
 Q    _______|‾‾‾‾‾‾‾‾‾|____
       master   slave copies at falling edge

A drawback is that J and K must not change while CLK = 1 (the master can "catch" a 1), so the inputs should be stable during the high period.

A J-K flip-flop is a clocked flip-flop with inputs J (set) and K (reset). Unlike the S-R flip-flop, the input J = K = 1 is allowed and makes the output toggle.

Logic diagram

Edge-triggered J-K using NAND gates; CLK* is a narrow pulse made at each rising edge of CLK by an edge detector (CLK ANDed with its delayed complement):

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

      +---------+
 J ---| J     Q |--- Q
 CLK -|>        |
 K ---| K    Q' |--- Q'
      +---------+
 '>' = edge triggered (a bubble 'o>' means
 negative edge triggered)

Operation

• J = K = 0: G1, G2 disabled, latch holds the state.
• J = 0, K = 1: at the edge G2 gives 0 (if Q = 1) and resets: Q = 0.
• J = 1, K = 0: at the edge G1 gives 0 (if Q = 0) and sets: Q = 1.
• J = K = 1: the gate with the 1 feedback fires, the output toggles once per edge.

Characteristic table

Characteristic equation

K-map for Q+ (rows Q, columns JK)
Q\JK   00  01  11  10
 0      0   0   1   1
 1      1   0   0   1
 Groups: J.Q' (row 0, cells 11,10)
         K'.Q (row 1, cells 00,10)

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Excitation table

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__

An S-R (Set-Reset) flip-flop is a clocked bistable circuit with inputs S and R. When the clock is active, S = 1 sets Q to 1 and R = 1 resets Q to 0; S = R = 0 keeps the old state; S = R = 1 is not allowed.

Logic diagram (clocked S-R using NAND gates)

          +------+  S*  +------+
 S -------| NAND |----->| NAND |-----> Q
 CLK --+--|  G1  |  Q'->|  G3  |
       |  +------+      +------+
       |  +------+  R*  +------+
       +--| NAND |----->| NAND |-----> Q'
 R -------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 form a cross-coupled NAND latch.

      +---------+
 S ---| S     Q |--- Q
 CLK -|>        |
 R ---| R    Q' |--- Q'
      +---------+

Operation

G1 and G2 are steering gates; G3-G4 is an active-low NAND latch.

1. CLK = 0: G1 = G2 = 1, the latch holds: no change whatever S and R are.
2. CLK = 1, S = 0, R = 0: G1 = G2 = 1, no change.
3. CLK = 1, S = 1, R = 0: G1 = 0 makes G3 output 1: Q = 1 (set).
4. CLK = 1, S = 0, R = 1: G2 = 0 makes G4 output 1: Q' = 1, Q = 0 (reset).
5. CLK = 1, S = R = 1: G1 = G2 = 0, both Q and Q' become 1: invalid. When the clock goes low, the final state is unpredictable.

Characteristic table

Characteristic equation

K-map for Q+ (rows Q, columns SR)
Q\SR   00  01  11  10
 0      0   0   x   1
 1      1   0   x   1
 Groups: S (columns 11,10)
         R'.Q (row 1, columns 00,10)

$$Q_{n+1} = S + \overline{R}\,Q_n, \qquad \text{with } S \cdot R = 0$$

Excitation table

• 0 to 0: S = 0 (R may be 0 or 1).
• 0 to 1: set, S = 1, R = 0.
• 1 to 0: reset, S = 0, R = 1.
• 1 to 1: R = 0 (S may be 0 or 1).

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
S     ‾‾‾|___________|‾‾‾|____
R     _______|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|_______|‾‾‾|__

Q goes to 1 at the edge where S = 1, to 0 at the edge where R = 1, and does not change where S = R = 0.

To make a J-K flip-flop work as an S-R flip-flop, we find J and K as functions of S, R and the present state Q. The S-R behaviour: SR = 00 hold, 01 reset, 10 set, 11 not allowed (don't care).

Step 1: excitation table of the J-K flip-flop

Step 2: conversion table

Step 3: K-maps

K-map for J
Q\SR   00  01  11  10
 0      0   0   x   1
 1      x   x   x   x

K-map for K
Q\SR   00  01  11  10
 0      x   x   x   x
 1      0   1   x   0

• For J: the only 1 is at Q = 0, SR = 10. Grouping it with the don't-cares in column SR = 11 and in row Q = 1 gives $J = S$.
• For K: the only 1 is at Q = 1, SR = 01. Grouping with the don't-cares gives $K = R$.

$$J = S, \qquad K = R$$

Step 4: circuit

          +---------+
 S -------| J     Q |--- Q
 CLK -----|>  JK    |
 R -------| K    Q' |--- Q'
          +---------+

So S is connected straight to J and R straight to K. Check: SR = 10 gives JK = 10 (set), SR = 01 gives JK = 01 (reset), SR = 00 gives JK = 00 (hold), which is the S-R table.