SIPO register with 1001 data

In a serial-in parallel-out (SIPO) shift register, bits are fed one by one into the first flip-flop and shifted along at every clock; once all bits are in, they are read at the same time from the outputs of all flip-flops. For the 4-bit sequence 1001 we need four D flip-flops with a common clock.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1001

The register is first cleared (0000). The data is applied LSB first, so the serial input is 1, 0, 0, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1001, which is 1001 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾|_______|‾‾‾|________________
QA    _|‾‾‾|_______|‾‾‾|______________
QB    _____|‾‾‾|_______|‾‾‾|__________
QC    _________|‾‾‾|_______|‾‾‾|______
QD    _____________|‾‾‾|_______|‾‾‾|__

So storing 1001 takes 4 clock pulses (input 1, 0, 0, 1, since 1001 is the same read either way), and retrieving is done in one step by reading QA QB QC QD = 1001 in parallel.