4-bit SIPO register with 1010 data

The question names the register SIPO, so it is explained here as a 4-bit serial-in parallel-out shift register. It accepts data one bit per clock at a single serial input and gives the whole word on four parallel outputs QA to QD. Its last output QD also works as a serial output, so the same circuit acts as a SISO register when the bits are taken out from QD by further clocks.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1010

The register is first cleared (0000). The data is applied LSB first, so the serial input is 0, 1, 0, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1010, which is 1010 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|________________
QA    _____|‾‾‾|___|‾‾‾|______________
QB    _________|‾‾‾|___|‾‾‾|__________
QC    _____________|‾‾‾|___|‾‾‾|______
QD    _________________|‾‾‾|___|‾‾‾|__

Note the serial output at QD after clocks 4, 5, 6, 7: 0, 1, 0, 1 (1010 read LSB first), which is the serial-out mode of the same register.