SIPO with 1010 data up to 9th clock

A serial-in parallel-out (SIPO) shift register takes data serially, one bit per clock pulse, into the first flip-flop and shifts it along the chain; the outputs of all flip-flops are available together, so after n clocks an n-bit word can be read in parallel.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Four D flip-flops share a common clock. $D_A = D_{in}$, $D_B = Q_A$, $D_C = Q_B$, $D_D = Q_C$, so at every rising edge each stored bit moves one stage right, and QA..QD are taken out as parallel outputs.

Function:

1. Clear the register (0000).
2. Apply the bits at Din, one per clock, LSB first.
3. After 4 clocks the word sits in QA QB QC QD and is read at once.
4. Further clocks (with Din = 0) push the data out through QD and the register clears.

Shift mechanism for 1010 (up to 9 clocks)

Serial input = 0, 1, 0, 1 at clocks 1 to 4 (1010 LSB first), and 0 afterwards.

• Clock 4: QA QB QC QD = 1010: the word 1010 is stored and read in parallel.
• Clocks 5 to 8: the data moves out through QD. QD after clocks 4, 5, 6, 7 is 0, 1, 0, 1 (1010 read LSB first), and the register is clear after clock 8.
• Clock 9: all outputs remain 0000 since only 0s are entering.

Timing diagram

       1   2   3   4   5   6   7   8   9
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|____________________
QA    _____|‾‾‾|___|‾‾‾|__________________
QB    _________|‾‾‾|___|‾‾‾|______________
QC    _____________|‾‾‾|___|‾‾‾|__________
QD    _________________|‾‾‾|___|‾‾‾|______